Re: OT Interesting power requirements... MORE

The message <go5jh4tbeuuol447p4rrdu90vu4tlnocut@xxxxxxxxxxxxxxxxxxxxxxx>
from Jaimie Vandenbergh <jaimie@xxxxxxxxxxxxxxxxxxxxx> contains these words:

On Tue, 11 Nov 2008 14:01:41 -0000, Daniel James
<wastebasket@xxxxxxxxxxxxxxxx> wrote:

In article
news:<4e4a7bed-9cf3-44c3-840c-30532bd483ef@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
, Westom1@xxxxxxxxx wrote:
CMOS battery must fails just as fast with power off as with power
always on. These batteries do not fail from power consumption. In
standby or power off, the battery discharges at the same rate - called
an internal discharge rate or sometimes called shelf life. If a
battery fails faster with power removed, then the motherboard has a
design defect.

So ... you're saying that the CMOS battery doesn't discharge any faster
when it is doing work powering the CMOS chip than when it is doing
nothing and the CMOS is powered by the PSU?

It's not really powering the CMOS chip, just providing a voltage to
hold the memory pattern.

It wouldn't surprise me if the difference between charge used and
charge leaked away over time was negligable - ie the battery
discharges at much the same rate whether the power is on or off.

That seems to be the reasoning behind our gmail poster's fallacious
conclusion. Even if we take an extreme case of a half microamp load by
the cmos (based on a CR2032 180mAH nominal capacity lithium coin cell)
of a service life that starts to approach 4 times the shelf life, the
discharge rate will still be reduced whilst the 5vsb line is active.
Mind you, at this sort of time scale, it all becomes somewhat academic.
;-)

--
Regards, John.

Please remove the "ohggcyht" before replying.
The address has been munged to reject Spam-bots.

.

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