Re: why does ddr333
- From: q_q_anonymous@xxxxxxxxxxx
- Date: 9 Aug 2006 21:44:08 -0700
Dwayne wrote:
hello everyone why does ddr333 run at 166mhz i thought its ment to run at
333mhz
you named it right. DDR 333 <-- not 333MHz
there are 2 terms.
Actual Speed - 166MHz
Effective speed - 333 'MHz'
marketting or others may call it 333MHz but I think that's technically
wrong
1 Hz is a clock cycle. It goes HIGH LOW HIGH LOW HIGH LOW - alternates
between a higher and a lower voltage I think.
The clock produces a "wave" if graphed on paper , because it's high
for a while, then it goes low, and is low for a while. So there are
events. "it's high", "it's dropped(dropping?) to low", "it's low",
"it's risen(rising?) to high", "it's high " e.t.c.
high=peak low=troph. like a wave. physics wave terminology
note-(in physics, frequency is things per second. "Time period" is
seconds for a thing. one is the inverse over the other(1/.. - one over
the other. Hz is frequency - cycles a second )
And given any of these events, a bit can be sent.
high,low,rising,falling(4 events)
a cycle is a peak to a peak or a troph to a troph (and, 2 others
involving risings and fallings (falling to falling, rising to rising)
). However you measure a cycle, every cycle has one peak, one troph,
one fall(peak to troph), one rise(troph to peak).
I think, old system, (before dual or quad pumped buses and DDR RAM -
i.e. with SDR RAM). Typically, a bit was sent onto the bus like on
every peak. (every cycle has one peak so
With dual pumped, it is peak and troph.
with quad pumped, it's peak,troph,rise,fall.
AMD Athlon XP, is a Dual pumped processor. P4 is quad pumped.
Meaning, that's how it deals with the bus. sending 2 bits per cycle, or
4 bits per cycle.
You have to get the concept of an FSB. The P4 and the AMD Athlon XP,
and probably most computers before the Athlon 64, had this set up.
(FSB)
CPU---------------------Northbridge
|
| (Memory Bus)
|
RAM
CPU and RAM aren't directly connected .There are 2 buses there.
I could be very wrong here, but
The way I see it, AMD Athlon XP goes well with DDR RAM.
P4 can also go well with DDR RAM, because DDR RAM often has another
functionality(not DDR), but dual channel. Where if you use 2 RAM sticks
(prob not just one double sided one?). Then the MBRD can do some mumbo
jumbo and effectively double the bandwidth of the memory bus , and, I
can't realyl remember, check some overclocking forums, but I think
it's like 4 times is sent! at the RAM end and so this matches the P4
end which quad pumps the FSB. So the bits sent at the RAM and and CPU
end are matched - equal amount sent, buses usually same speed or at
least effective speed, no bottleneck.
I've also heard that whether dual channel is used or nto doesn't make
much difference. but if you do the maths it looks like it does - to
balance the bandwidth of the fsb and memory bus.
The places I read about this -
- howstuffworks article on MBRDS - had a good diagram with FSB and
memory bus.
- overclocking forums - always discussing DDR, FSB, bottlenecks
- GCSE physics I remember a little about waves
- looking in my BIOS and setting the RAM speed and underclocking my
CPU by lowering the FSB..
- usenet archive (Google groups)
I'm not suggesting that you use those resources, but, i'm just giving
my references, bad as they are ;-)
.
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- From: Dwayne
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