Re: Altera Cyclone II DQ/DQS pins location ... other pins as well by the hardware, but the software does not support this). ... I have an issue with porting my high-speed DDR interface to Altera ... the Altera Cyclone II package as dedicated pins for DQ input/outputs? ... (comp.arch.fpga)
Altera Cyclone II DQ/DQS pins location ... I have an issue with porting my high-speed DDR interface to Altera ... Input/Output blocks for DQ pins.... So, it seams that we have only DQS pins location fixed,... the Altera Cyclone II package as dedicated pins for DQ input/outputs? ... (comp.arch.fpga)
Re: Altera Cyclone II DQ/DQS pins location ... I have an issue with porting my high-speed DDR interface to Altera ... Input/Output blocks for DQ pins.... So, it seams that we have only DQS pins location fixed,... the Altera Cyclone II package as dedicated pins for DQ input/outputs? ... (comp.arch.fpga)
Re: DDR Address ... Is it ok not to connect at least one DDR Address signal to a ddr ... My design is out of IO pins, BTW i use an FPGA ddr controller core..... number of data pins without losing memory. ... (comp.arch.fpga)
Re: DDR Address ... Is it ok not to connect at least one DDR Address signal to a ddr ... My design is out of IO pins, BTW i use an FPGA ddr controller core..... number of data pins without losing memory. ... (comp.arch.fpga)
