Re: Charles Murray "The Plan" ends poverty

Alvin E. Toda wrote:

On Sun, 8 Apr 2007, Islander wrote:

Alvin E. Toda wrote:

On Sat, 7 Apr 2007, Islander wrote:

Alvin E. Toda wrote:

On Fri, 6 Apr 2007, Islander wrote:

Alvin E. Toda wrote:

On Fri, 6 Apr 2007, Islander wrote:

Alvin E. Toda wrote:

On Wed, 4 Apr 2007, Islander wrote:

Alvin E. Toda wrote:

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This is interesting history. I'm sure someone will write about it someday. But I guess the general interest will be nil-- outside of program developers and users. It's too "nerdy" a topic.






The early days of electronic design automation are indeed interesting and if someone is going to write a history they had better hurry up. Some of the pioneers have already died.

Few people know, for example, that Marlon Wagner developed one of the first if not the first design automation program. This was in the late '50s and it was used to produce wiring lists for the NSA special purpose machines of that era. It ran on a machine called Bogart a vacuum tube machine built at NSA IIRC.

Cray published the first reference to Design Automation in a speculative paper published in an early computing conference where he predicted that one day computers would be used to design computers. I've got the citation around somewhere.

Gwen Hayes published the seminal paper on logic simulation reporting on a digital simulator that she wrote at Westinghouse in '62.

Ivan Sutherland developed the first Computer Aided Design graphics program at Lincoln Lab in 1962 -- Sketchpad

Donald Durr of RCA developed the first automated placement and wire routing program (PRF) for LSI circuits in '65, I think. This was funded by NSA based on knowledge of the work that Wagner had done earlier. NSA installed a Gerber photo plotter to produce masks at 200x and used a program called ARTGEN developed by *** Nodo of RCA which was a marvel in affine geometry. *** was nearly blind, but an amazingly creative programmer. Durr later went to work at NSA and worked for me during the '70s.

There was also work underway in automatic placement and routing at TI at the time. The developers knew about each other, but as far as I know the efforts were completely independent.

NSA was an amazing place in the '60s and '70s and was well ahead of the SoA. I wish that more of that work had been published, but the effort to get approval to publish at NSA was daunting. At one point, you had to get 15 signatures to approve publishing a technical paper.

SIGDA of the ACM has attempted to preserve all the early literature of Design Automation and has most of this on CDs. Unfortunately some of the earliest work was reported at meetings that had no proceedings and some of the work done at IBM, Bell Labs, and TI was considered to be confidential and was not published. I knew many of the pioneers from their participation in professional meetings in the '70s when I was active in various ACM and IEEE groups.






I think that you have just proved my point about the nerdyness of this history. Most would not identify with these historic milestones. I substitute teach and I would rougly estimate that 1% or less of the graduating class is going into sceience, math, or engineering in college. The overwhelming majority that will eventually go into a technical trade or engineering are those that go into the military and learn a skill there. There is not even a wood shop anymore. It's used for storage and health classes.

Regarding your history, I think that you should mention the sneak circuit analysis s/w that Boeing has. I heard about this about 25-30 years ago when it was a well established methodology with them. I've had some experience with large systems in which the wrong circuit bounce in a switch or relay could set some relays to chatter and the system to wildly respond. By experience technicians know which relays to tap with a screwdriver to stop the chatter and which switches or relays to replace to fix it-- not that there's anything wrong with the relay or switch.

BTW even a wrong replacement with make before break for a break before make switch could be disasterous. I would guess that the Airbus delay might be due to some of these sneak circuits? These sneak circuits might make their appearance at the bottom of the bathtub curve of wear for the relay. They tend to appear late. The early problems are caught by the design team during initial testing.

I think that the success of Boeing's airplanes have been their sensitivity to these types of problems and ability to get it right the first time. Wish I still had stock in the company. But for a while it seemed like Airbus was the future. I think that Airbus is an example, where good marketing, imagination and creativity gets zapped by the wrong screw in the right hole.





Interesting. I thought that anti-bounce circuitry was one of the first things that one learned on the job.

Speaking of relays, one of my first projects was to build a circuit test controller. I picked relays because of the variety of different circuit interfaces that were needed. I used about 100 relays configured as a two phase shift register. Each stage set up a particular test and the shift sequence could be programmed. It sounded like a sewing machine.

We built three of them and the tech who wired the back panels was a real artist. The wires were bundled perfectly parallel and laced neatly. He was the ultimate in believing that a job done well is a job done right.





You can't really stop relays and switches from bouncing. You just need to insure that they behave correctly despite the bounce-- for all possible transient positions of the switching relays. Capacitors slowed down the switching, and helped the bouncing, but nowadays there are processors polling relays without debouncing circuits to determine whether they have switched. Also, IIRC it is also possible with some marginal relays that more than one contact will be involved in the bounce.

But I agree whole heartedly with the tech. You have to be sure of the connections at each stage, because doing it right the first time is a lot more efficient than figuring each wiring error by debugging.




Back in the '60s I knew some people at GME who were great at designing MOS circuits for multi phase logic. One guy in particular had read up on ultra reliable circuitry that was developed for the railroads a half century before. Really creative stuff!




For two non-overlapping phases, a lot depended on the types of clocks that were generated. Some designs were dependent on a stable process and would have to be re-designed for each process. I liked the concept of three or more clocks that were not vulnerable to clock skew, but they were mainly limited to datapaths.

And if that "reliable circuitry" has anything to do with relay logic, or switches, then I wouldn't claim that to be the case. I've seen so much that can go wrong with huge bays of switching and relay boxes. ICs in comparison are much more reliable.



In the early MOS circuitry there was a lot of experimentation with switching charge from node to node and that was very similar to relay switching networks. We used four phase clocks (which were really two phase for switching and two phases for pre-charging nodes. This was primarily for PMOS and NMOS processes. When CMOS was introduced, the need to precharge nodes went away (or was only used for specialized circuits). The complementary transistor structures allowed the designer to always have a path to Gnd or Vcc.



I think the precharing was still used in datapaths. But I can't really say that in general. The N-channel transister was optimised for the process and the the P-channel allowed to be a big as it needed to be. Hence, you might see in pre-charged circuits a humongous P-Ch precharge and a lot of small N-Ch logic when it came time to switch the logic. The four phase clocks have only two for switching? I was thinking of a circuit which has say three clocks for switching where they might even overlap and still the circuit would work.


There was a lot of circuit creativity in those days and the version of four phase that I used had two phases for precharging nodes and two for switching. IIRC there was also four phase logic with four overlapping phases, but I never used it. I could imagine where three phases might also be used with switching 1/3 out of phase with the pass transistor.

When CMOS became available there was a lot of effort to continue to use the large logic arrays that were developed for NMOS. I was no longer designing circuits by that time, but wouldn't have been surprised to see circuits of that type in the textbook that Dobberpuhl wrote.

Clock distribution, especially for four phase logic was a major problem and led to some of the early work on self-timed logic that I mentioned earlier -- one of the Sutherland brothers and also work done at Cal Tech.


I believe I know the Dobberpuhl book. It's one of those basic reference works. IIRC the 3 and 4 overlapping phases are mentioned there. But I really like the section on rams. It was well done.

And regarding the self-time logic. I recall reading some papers from Cal Tech. The methodology is difficult to understand and too difficult for working engineers to use. The same can be said about multiphase logic. It would just be too complex to use in real-world circuits-- when designing by hand, I mean. But I understand that there is now software to convert synchronous logic to self-timed logic. It is proprietary and mainly used to conserve power. Clock switching takes so much power at the high clock speeds in use nowadays.

There are a lot of books on VLSI design now, but in the early '80s we needed a book to replace the Mead/Conway "Introduction to VLSI Design" which focused on NMOS. One of the tasks that I took on at DARPA in the early '80s was to move the universities from NMOS to CMOS. NMOS was clearly a dead end, but had built up a major head of steam because the Mead/Conway book was really the only good textbook. Prior to moving to DARPA, I had led a group at NSA that developed a 3 micron CMOS design rule set, qualified a group of manufacturers that could build that rule set, and developed the parametric test chip that could qualify the process. All of that was given to the university community by NSA.

We bootlegged a course for teachers at USC/ISI, taught by Chuck Seitz of CalTech in the summer of '84 and were running regular 3 micron CMOS runs through MOSIS in the fall. Meanwhile Lance Glasser was working on a text and joined with Dan Dobberpuhl to produce the final product, a little late, but published at last in '85. I think it is still widely used.

These were exciting and very heady days. There were a lot of very talented and highly motivated people involved. I've since kept in touch with some including Lance who is now VP Research at a semiconductor manufacturing equipment company.
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