JOB Opening: Sr. DFT Engineer- Semiconductor Solutions- Austin, TX
- From: "Dee Dee Dial, Executive Technology Recruiter" <dddial@xxxxxxxxxxxxxxxxxx>
- Date: Tue, 26 Jul 2005 15:04:28 GMT
Senior DFT Engineer
Contact:
Dee Dee Dial, Sr. Executive/Technology Recruiter
Pedley-Richard & Assoc.
Email: dddial@pedley-richard
Phone: 512/418-3260
(Note: all resumes are submitted in confidence and will NOT be
forwarded to any client company without the expressed consent of the
individual.)
SUMMARY:
Will be responsible for ensuring the testability of the products.
Needs to implement SCAN, BIST and other test modes required for this. Must
work closely with the test and product teams to ensure that all the test
requirements are met and there is a smooth flow to volume production. Will
need to work with test engineering and help in the debug and
characterization of first silicon.
FUNCTIONS / DUTIES / RESPONSIBILITIES:
a.. Implementation of test modes for mixed signal devices to enable
the complete testability of the part working with the design and test
engineering teams.
b.. Verification of all the test modes in RTL and gate simulations
c.. Implementation of full scan.
d.. Generation of scan vectors using ATPG, and simulations on the
gate netlist to verify the timing of the scan path.
e.. Implementation of BIST engines as required and verification of
the operation of these in RTL and gate level.
f.. Generation of functional tests as required to enhance test
coverage.
g.. Conversion of all simulation output to vectors for the tester.
h.. Debug of first silicon and validation of all test modes in the
product.
i.. Incorporation of test modes to enable known good die testing
taking into account the limitations with testers at wafer sort.
REQUIRED EDUCATION / SKILLS / EXPERIENCE:
a.. BSEE
b.. Experience in DFT and DFT tools
DESIRED EDUCATION / SKILLS / EXPERIENCE:
a.. BSEE/MSEE
b.. Knowledge of ATPG tools from Mentor and Synopsys
c.. At least 5 years experience in DFT implementation for mixed
signal device
d.. A good knowledge of Verilog simulation and test benches
e.. Experience in debug of RTL and gate simulations
f.. Knowledge of testers and experience in debug of first silicon
.
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