100nF load stability issue
- From: "Marcin Slawicz" <mslawicz@xxxxxxxxxxxxxxxxxxxxxx>
- Date: Sat, 5 Nov 2005 14:38:42 +0100
My first tube amplifier project is almost completed, however I have doubts
about its hf stability.
This is a Williamson circuit with UL power stage and somewhat modified front
end (John Broskie's Aikido style voltage stage with concertina phase
splitter).
The first stage is ECC82 (V1) with ~600 ohm cathode resistor and 22k plate
resistor. The amplifier open loop gain is 88.5 @ 1 kHz (38.9 dB).
Feedback loop is Rf=9.88k connected to V1 cathode (15.7 dB).
The amplifier has a toroidal OPT with estimated f3=70 kHz (measured by
someone else, however I don't know which way).
So, the lowest pole in hf range comes from the OPT (lets assume 70 kHz).
The second pole is from driver stage: 110 kHz (6SN7, gain 16, driven from
concertina plate side Rout=21k).
The third pole is at input stage: about 800 kHz.
Next poles come from output 6L6GC (1.6 MHz) and concertina splitter (3 MHz),
and can be probably ignored in a well stabilized amplifier.
According to my estimations, the uncompensated amplifier has dominant pole
(at least with nominal resistive load) at 70 kHz and the next one at 110
kHz. At 200 kHz the loop gain drops to unity with the phase margin about 30
degrees. The amplifier should be conditionally stable.
Indeed it is. However with anything but the nominal resistor at the
output the circuit starts to oscillate.
Then I used two compensation circuits:
RC lag compensation (R1=4k7, C1=390p) parallel to V1 plate resistor. This
should put a new dominant pole at f=23 kHz and zero at 110 kHz.
Lead compensation - C2=56p across feedback resistor. This should put a new
zero at 130 kHz and a pole at 11 MHz. The main goal is to dump the square
signal overshoot and ringing.
These two networks should give me a dominant pole at 23 kHz, the next one at
70 kHz from OPT (however this one can move), and the third one at 110 kHz
compensated with zero from the lag compensation network. I expect the unity
loop gain at about 90 kHz with something like 50 degrees phase margin.
The amplifier stability should be OK, however real life is much more
complex, so I wanted to test the stability the way Patrick has advised so
many times.
I used a 10k pot as the R1 and prepare the circuit to be able to easily
change both capacitors during the tests. I also used 5 kHz square wave
generator for testing.
My results are as follows:
1) 8 ohm resistive load - no stability problems.
2) No load - tested with C1=130p, 390p, 1n. Stable with R1<6k for low output
amplitude, R1<9k for high output amplitude.
3) Speaker load - stable with R1<5k5.7k5 (output amplitude dependent).
Optimal R1=4.5k.
4) Capacitor 0.22.1 uf load - stable with any used value of C1 and R1.
Optimal R1=5k5.10k (output amplitude dependent).
5) Capacitor 100n load - stable with R1<3.3k5 only.
6) Capacitor 47n load - stable with R1<1k5.2k only!
7) Any capacitor parallel with 39 ohm (or lower) load - stable with any used
R1 and C1 value.
The amplifier stability depends most on the R1 value.
C1 and C2 exact value much less contribute to the overall stability, however
C2 helps to dump pulse overshoot and ringing. Too much C2 leads to
instability though.
The values I estimated before testing (R1=4k7, C1=390p, C2=56p) seem to be
right and provide good amplifier stability with almost any kind or without
load.
The only problem is the possibility of oscillations with the 47nF or 100nF
cap as a sole load.
Should I worry about it?
Is the amplifier stable enough?
I should add, that my speakers the amplifier is to be working with, are a
kind load for it. Their impedance peak is only 21 ohm (bass region), and 7.9
ohm with any frequency above 200 Hz.
Cheers,
Marcin
.
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