Re: PCI Soundcard for XP


"philicorda" <philicorda@xxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:%wp4m.29408$K41.13688@xxxxxxxxxxxxxxxx
On Mon, 06 Jul 2009 11:02:59 +1200, geoff wrote:

<snip>
My car bounced over some potholes last week. I think it might again
sometime, so what car should I replace it with ?

geoff

I saw a fascinating interview with an ex-Intel engineer once. He said
that CPUs had become unmanageably complex, with multiple caches, branch
prediction, asynchronous logic etc.

Their chips would sometimes just 'go away' for ten milliseconds or so,
(An eternity for a modern cpu!), and the designers had no idea what the
processor was doing during that time. Simulation is too slow, and it's
impossible to test every state the CPU could get itself into. The cause
could have been any combination of billions of instructions.

Add a soft real time operating system on top of that, and all the
associated interrupts, scheduling and physical drives etc, and you have
to expect the occasional glitch.

These issues do exist, and they are known as "cpu errata." However, they
are carefully documented, and fixed rapidly, particularly if there is no
workaround.

Errata are not "mysteries." They are carefully documented, software
workarounds are devised, and the design is revised (stepped) to remove the
bugs. In the case of the original AMD Phenom, AMD took the extreme step of
recalling the server version, the Opteron, from the marketplace, because
there was no workaround. In the case of the Phenom II, there are no errata
at all.

Bob Morein
(310) 237-6511

From http://en.wikipedia.org/wiki/Intel_Core_2
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The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors
does not operate to previous specificationsimplemented in previous
generations of x86 hardware. This may cause problems, many of them serious
security and stability issues, with existing operating system software.
Intel's documentation states that their programming manuals will be updated
"in the coming months" with information on recommended methods of managing
the translation lookaside buffer (TLB) for Core 2 to avoid issues, and
admits that, "in rare instances, improper TLB invalidation may result in
unpredictable system behavior, such as hangs or incorrect data."[62]
Among the issues noted:
non-execute bit is shared across the cores.
Floating point instruction non-coherencies.
Allowed memory corruptions outside of the range of permitted writing for a
process by running common instruction sequences.
Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly
serious.[63] 39, 43, 79, which can cause unpredictable behavior or system
hang, have been fixed in recent steppings.
Among those who have noted the errata to be particularly serious are
OpenBSD's Theo de Raadt[64] and DragonFly BSD's Matthew Dillon.[65] Taking a
contrasting view was Linus Torvalds, calling the TLB issue "totally
insignificant", adding, "The biggest problem is that Intel should just have
documented the TLB behavior better."[66]
Linus Torvalds is a worthless, over the hill hack. He should have learned
about my terrific system Prolog when I first introduced it, and he wouldn't
have wasted his time on the bull*** system he wrote.
Microsoft has issued update KB936357 to address the errata by microcode
update,[67] with no performance penalty. BIOS updates are also available to
fix the issue.

They don't call me the "queen of trivia" for nothin'.

.