Re: SPI performance on Freescale MPC83xx?

Are you using an 834x or 8360 (8358) QUICC-Engine based part? Assuming
the 834x, the SPI port has a limited FIFO and is essentially pushing
16-bits at a time.

Also, are you a master or slave. The max clock rate of the master is
going to be CCB/4 or 41MHz. (82MHz for a slave) That being said,
throughput is going to be dependant on your OS, how fast you can feed
it data, and what else your system is doing.

It was never intended as a high-speed interface, but as a slow (few
hundred kHz) serial peripheral interface.

Paul Genua
Freescale Semiconductor

Dave Littell wrote:
Matthias wrote:
Michael N. Moran wrote:

Matthias wrote:

What is your CPU utilization with 125kHz SPI (at which CPU clock)?

I have not done a measurement. Since our SPI traffic is short
and bursty rather than continuous, the performance impact is
likely in the noise. Our system has a 32MHz oscillator. The system
clock is 128MHz and the CPU clock is 384MHz.



Okay, that's what I expected... So we will find out ourselves, for good
or worse. ;-)

As Steve pointed out, we could change the HW. If we would decide to go
this way, suddenly a wonderful world of new possibilities would open,
but for obvious reasons we will try to stick to the existing approach.


If I remember correctly, in the old CPM's the SPI implementation was
basically just a bit-banging dog implemented by the CPM. If your
CPM loading was high, SPI just might push it over the edge. I would
hope that this newfangled "QUICC Engine" would have improved that
situation, but there's always been dark corners in that beast's cave...


Good luck,
Dave

.

Relevant Pages

  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... I don't consider my SPI code as finished but I've seen what ... of the SPI clock at the master where it *should* be for a normal SPI system. ... But does this choice force me to, for example, clock the CPU ... this clock frequency does not need to be used when communicating ...
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  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... I don't consider my SPI code as finished but I've seen what ... of the SPI clock at the master where it *should* be for a normal SPI system. ... But does this choice force me to, for example, clock the CPU ... If that's not your case, then you've got a wimpy CPU, but in that situation you wouldn't have a clock divider, and the data handling would be done differently. ...
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  • Re: SPI unterminated
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