Re: I can't drive 95....


"Louis Ohland" <ohland@xxxxxxxxxxx> wrote in message
news:9xJXh.22$lU3.10@xxxxxxxxxxxxxxx
Hmm, by increasing the xtal and using a larger division factor, could we
provide a more stable upper PEL frequency?

Louis Ohland wrote:
Smoking whiskey, drinking cocaine... I got me a feeling, XGA is driving
me insane...

UZ, XGA-2 has a whoppin' 4MHz xtal on it, probably to act as a reference
for the internal PLL.

Assume that the PLL is designed for stability. The division factor
applies to the PLL output, NOT the 4MHz reference. So the PLL native
output is 16x to 32x of the xtal.

90.00 x DF - 65 = 25

Oddly, for a PEL freq of 65MHz, the index would be 0, and for 128MHz,
the index would be 63.

Louis Ohland wrote:
> Frequency Index = (f × Division Factor) - 65
where f is the PEL Frequency required.

FR Field Division Frequency Range
(binary) Factor

0 0 4 16.25MHz to 32.00MHz in 0.25MHz increments
0 1 2 32.50MHz to 64.00MHz in 0.50MHz increments
1 0 1 65.00MHz to 128.00MHz in 1.00MHz increments
1 1 - Reserved

Louis,

I wouldn't count on it. PLLs are members of the bad analog world (in my
opinion) but we rely on them to fix up some of the timing mess that we
encounter in the perfect digital world. Part of their operation is guided by
some filter on the phase comparator. Increasing the reference frequency by a
factor of 4 may displease the PLL in question. Only a datasheet can tell (or
simulation or trying).

The way the frequency generator is built seems to be the following (rather
conventional):

+---> PEL CLK
|
+--------+ +-----------+ | +--------+ +------+
| fixed | | PLL | | | pre- | | var |
4MHz --->+ DIV 16 +------>+ ref out +-+->+ scaler +--->+ DIV +--+
| | | | | 1/2/4 | | 1-64 | |
+--------+ +-->+ feedback | +--------+ +------+ |
| | | |
| +-----------+ |
| |
+--------------------------------------------+

The reference frequency is 0.25MHz. The divider's factor is it's programmed
value + 1 (classic down counter architecture).
The principle is that the PLL will try to match the divided PEL CLK's phase
with the incoming reference frequency of 250kHz (and have the same frequency
as a consequence). In principle, you can interchange the pre-scaler and var
divider, but pracically, you'd keep the complex divider at the lower
frequency range.

Going above 100MHz with CMOS outputs is today still unlikely, so with logic
of the 90's, I'd say close to impossible. TTL will give up sooner. ECL,
LVPECL could have been used for the high speed logic (RAMDAC, serializer)
but main logic would then have run at a lower frequency. Are the extension
connectors single ended (PIX[7-0], H, V) or differential (PIXp[7-0],
PIXn[7-0], Hp, Hn, Vp, Vn)?

Alvin.




.

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