Re: talking to CTK 571 synthesizer

Previously Allan Adler <ara@xxxxxxxxxxxxxxxxxxxx> wrote:
Arno Wagner <me@xxxxxxxxxxx> writes:

Allan Adler writes:
I decided I should also bring with me my copy of M.Morris Mano's
book on digital logic and computer design and my copy of the 2d
edition of the TTL Data Book from Texas Instruments. What I'd like
to do is try to imagine how to convert the block diagrams into an
actual design of a UART from components in the TTL Data Book, for
example, just in case it is not already in there itself. That should
do a lot to clarify the universal functionality.

I think that is a good approach. An UART is still simple enough
for that to be feasible.

I did some searching on the net for uart design and found that this
seems to be a standard lab exercise in some courses, but maybe not
with real chips. Also, I found some stuff on languages for carrying
out such designs. One article on the topic mentions compiling down
to Register Transfer Language, which is one of the things I was
planning to look at in M.Morris Mano's book (RTL, not compiling down
to it), but also gives the impression that RTL itself isn't flexible
enough. It has references to online sources of information about
some of these languages, but I don't know whether any of them is
available for free or could be installed on my system. One lab I
found online refers students to the Xilinx library. I haven't tried
to access it yet. But I'll try the design with TTL chips naively in
my own way and not get distracted with these other interesting
tools.

I have a bit (very limited) experience with some design languages.
My impression is that they confuse the issue. I think they are
more write-only languages and only intended to be read by machines.

Since the primary goal is to write the root sector, I gave priority
today to trying to make sense of interrupts on the UART. Thanks to
your helpful remark about how to write to the registers, I think I
have a plan but I'm not sure it is correct. I'll write the actual
program tomorrow. Here is the plan: Of course, I have to write to
the THR. On p.24 of the spec sheet, it says that the ACE transmitter
consists of the THR and a transmitter shift register. Timing is
suppled by the baud out clock signal. For the moment, I'll assume
the baud rate is what it needs to be for MIDI. If not, there will be
something else to do before what I'm about to describe, namely
writing to some registers that control the divisor of the clock
rate. Transmitter control is a function of the Line Control
Register (LCR). I think I want 8 bit words to be sent, so bits 1,2
of the LCR should be 1. Since writing THR requires DLAB to be 0,
and since DLAB is bit 7 of the LCR, I certainly want bit 7 to be
0. I'm assuming that the other bits don't matter unless I want to
worry about them. So, I basically want to write 0x3 to the LCR. The
bytes I want to send to the Casio CTK 571 are 0x90 0x40 0x7F. I
don't want them to arrive in the THR before they are ready to be
transmitted, so I think I want to enable the Transmitter Holdering
Register Empty interrupt by setting bit 1 of the Interrupt Enable
Register (IER).

I think for the first experiments you should poll whether the
data has been sent in a loop. Interrupts add their own level
of complexity, better get to that later. Writing an
interrupt service routine can be tricky.

So, I want to write 0x2 to IER. In order to detect
when that interrupt has been triggered, I need to look at the register IIR
until bits 2,1,0 of it are respectively 0,1,0.

Actually you need to install an interrupt service routine, that
will be called by your computer's hardware when the interrupt
is sent. Maybe you can disable interrupt output (hardware
ouput line) and poll the IIR nonetheless.

Therefore, the plan is:
(1) Write to LCR (Port 0x333) and put 0x3 in it.
(2) Write to IER (Port 0x331) and put 0x2 in it.
(3) Write to THR (Port 0x330) and put 0x90 in it.
(4) Repeatedly read IIR (Port 0x332) until it contains 010 in the 3 least
significant bits.
(5) When it contains 010, that signifies that THR is empty. Then write
0x40 to THR (Port 0x333).
(6) Repeatedly read IIR (Port 0x332) until it contains 010 in the 3 least
significant bits.
(7) When it contains 010, that signifies that THR is empty. Then write
0x7F to THR (Port 0x333).

Sounds reasonable. Also a good first test setup. I assume
0x90 0x40 0x7F plays a note.

Arno
.

Relevant Pages

  • Re: talking to CTK 571 synthesizer
    ... book on digital logic and computer design and my copy of the 2d ... edition of the TTL Data Book from Texas Instruments. ... One article on the topic mentions compiling down to Register Transfer Language, ... I have to write to the THR. ...
    (comp.sys.ibm.pc.hardware.misc)
  • Re: Interrupt mechanism in "PCI to Serial driver" fails in WinCE 5
    ... it will clear that particular interrupt. ... Generally your bsp should have an structure declared to your serial port ... value of IER for THR. ... of IER register" and second parameter as the value 0x2(will set IER for THR ...
    (microsoft.public.windowsce.platbuilder)
  • Re: Interrupt mechanism in "PCI to Serial driver" fails in WinCE 5
    ... I am not sure about KITL sharing the IRQ but with respect to your ... it will clear that particular interrupt. ... value of IER for THR. ... How can i register the interrupt in CEPC for my device. ...
    (microsoft.public.windowsce.platbuilder)
  • [patch 2.6.27-rc8-git] add drivers/mfd/twl4030-core.c
    ... This patch adds the core of the TWL4030 driver, ... There are some known issues with this core code. ... * often at around 3 Mbit/sec, including for interrupt handling. ... and exports register access primitives. ...
    (Linux-Kernel)
  • Re: Blue Chip Technology + MagnumX?
    ... store 1 byte pin state register and 32 bit counter value. ... refreshed and depending on the type this is done autmatically by hardware ... See above about code in interrupt handler and performance issues. ... Get the designer of the board generating the digital inputs to ...
    (comp.arch.embedded)