Re: IBM's new memory latency reduction technology for Opterons


"David Kanter" <dkanter@xxxxxxxxx> wrote in message
news:1155339400.429807.6590@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I'm not an idiot Keith. It is patently obvious that the POWER5
memory
controller is proprietary. My point is that the buffering that IBM
uses in the pSeries and X3 could probably be modified to work for an
Opteron OR any other system IBM sells. I suspect that this is how
they
are able to have heavily populated memory channels.

You've done a great job of fooling me. You said "migrated this
technology down to Opteron system boards". With one they have
control over at least one end of the interface. Not so with the
other.

So why don't you explain to me (and everyone else) how they differ
technically instead of waving your hands in the air and asserting that
you somehow know better. Or maybe you can't share that information?

Why is control of the interface a requirement for a buffering solution?

Do you know for a fact that Power5 uses some magical "buffering"
technology that would be transferrable to Opteron? No, you're
talking through your hat.

Literacy doesn't seem to be a strong point for you:

"My guess is that they
migrated this technology down to Opteron system boards... "

"My point is that the buffering that IBM uses in the pSeries and X3
could probably be modified to work for an Opteron OR any other system
IBM sells. I suspect that this is how they are able to have heavily
populated memory channels."

Did you notice the word "could" in there? I referred to this as a
guess or possibility, not a fact. I'll be waiting for an apology...

Quoting from IBM's redbooks:

The p5-590 and p5-595 memory controllers are internal to the POWER5
chip. The memory
controller interfaces to four Synchronous Memory Interface II (SMI-II)
buffer chips and eight
DIMM cards per processor chips, as shown in Figure 2-11 on page 29.
There are 16 memory....

So why don't you explain to me why you cannot use memory buffering for
an Opteron? In particular, it seems to me like IBM already has this
technology down for use with the P5+ memory controller.

If you could comment on the substance of my posts, rather than
details
which you misinterpret, I'd appreciate it.

Perhaps you should read what you write. It makes no sense.

Keith, I'd like to thank you for bringing so much maturity and
technical facts to this discussion. This group is so much richer for
it...

DK

The memory controller in Opteron isn't designed with SMI in mind, like
the power5 one is. Or power4 for that matter.

This thread has been marked by a great deal of uninformed speculation.
Could IBM have used SMI in conjunction with the Opteron controller? It
should be possible to figure that out since the controller is well
documented, and evaluating how to buffer it for more loads should be
fairly straightforward.

Instead you chose to engage in uninformed speculation. The use of SMI
should be readily detectable by looking at actual hardware or pictures
thereof. Latency or access time specs should also be good measures.



.

Relevant Pages

  • Re: IBMs new memory latency reduction technology for Opterons
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