Re: AMD to produce ATI GPUs in Dresden

[snip]

This "bad idea" has been done before.

When and where? Did they hit their release targets?
Were there any yield issues?

IBM. I'm not going to get into specifics.

So you won't say whether or not it turned out to be a horrible idea?

I would expect that if they wanted to switch over
they would start with designs that haven't done much PD. My rough
estimate is that the design time for a GPU is 3 years, and PD probably
starts after 1 year. After they start PD, I don't think they'd
retarget.

Have you ever *done* this? Me thinks you're talking though your
hat, again.

No I haven't, I'm not an EE. If you have a timeline you'd like to
suggest, go ahead...

I already did. Less than a year, assuming a good design.

What constitutes a 'good design'?

Pick one set of "books"
instead of another. Circuit design is different (presumably AMD
already has the necessary circuits), and processing is different,
but one logic chip looks pretty much like the next.

AMD has the necessary circuits, but ATI engineers have no experience
with them. That's just asking for trouble, even if you have AMD
circuits guys coaching them along. Delays for CPUs are bad, but for
GPUs they are brutal, since the life time is so much shorter.

One doesn't need "experience" with a circuit to use it.

I don't really buy this argument. Mainly because you are going to be
constantly tweaking your circuits to get better performance, lower
power or ideally both. That means you have to know what is going on in
circuit land...

Of course you don't buy into reality. Logic designers don't tweak
circuits. They select books the circuit designers have already
qualified. One doesn't go messing with circuits once the logic is
cast. Can you say "chase your tail"?

So what happens if your target frequency is say, 600MHz, and it turns
out you can only hit 400MHz, but you have 3-4 months before tape out?
Do you just sit on your ass and let the circuits moulder? Or do you,
perhaps, start tweaking things to get improvements, track down critical
paths and fix them?

Or do you perhaps go back to the logic guys and say: "Hey, you blew a
lot of timing on this one chunk, could we try something quicker..."

Logic is
logic, fer chrissake. The biggest problem with SOI is getting the
circuit designs right.

And yields...

Remember, AMD has a mature SOI process. The yield thing isn't part
of the equation.

I'm not really that sure. Acceptable yields for a 100mm^2 die may be
unreasonable for a 350mm^2 die, especially considering that GPUs have a
much higher density of logic, which is going to be more vulnerable to
defects. For a CPU, you at least have a pretty good chance of hitting
cache, which is easy to fix.

Considering that GPUs take at least 3 years to design, I think the
earliest that this could happen is 2 years from now (assuming that
there is a design that started 6-12 months ago, and was still in
architectural phase and hadn't done any actual physical stuff).

It would take less than a year to migrate a design form bulk to a
mature SOI process.

Can you elaborate? Do you mean a design that is already in bulk
production? Or do you just mean a taped out bulk design?

Either way. Assuming no silicon (though metal changes may be
necessary) respins for logic errors, to SOI production volumes.
This would include hardware verification and perhaps two passes
(engineering then production) through silicon. The switch may be
transparent for a design already in the pipe, though logic errors
are an issue on a new design.

Also, how big a design are we talking about? GPUs are not as tricky as
CPUs, but they are some of the larger and more complex ASICs out
there...

My experience is with CPUs, so calibrate from there. According to
your assumption, migrating a GPU to SOI is a walk in the park.

I think you're putting words in my mouth.

I'm saying that generally CPUs are more complex than GPUs; certainly an
ARM7 isn't as complex as the most modern GPU, but...as a general rule
of thumb, a CPU is going to be more complex than a GPU.

I would agree that porting a GPU to SOI should be easier than porting a
CPU, especially since *on average* you have less custom design work.
However, I think characterizing either as 'trivial' is silly.

If you are saying you can port a SCSI controller from bulk to SOI in a
year, then I'm not sure that means much. I'm hoping you are talking
about a substantial design...

Now really, a SCSI controller in SOI would be rather silly, no?

Sure, but I don't know what kind of design you were working on, and you
haven't chosen to share that information. Therefore, I can't really
come to any conclusions about whether your experience porting is
closely correlated to that of a GPU, a lower bound, an upper bound,
etc...

In other words, I need more info!

DK

.

Relevant Pages

  • Re: AMD to produce ATI GPUs in Dresden
    ... AMD has a mature SOI process. ... a design from bulk to SOI. ... CPU>> GPU ...
    (comp.sys.ibm.pc.hardware.chips)
  • Re: AMD to produce ATI GPUs in Dresden
    ... Were there any yield issues? ... within the parameters I've mentioned (mature SOI ... process, working design). ... migrating a GPU to SOI is a walk in the park. ...
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  • Re: AMD to produce ATI GPUs in Dresden
    ... process, working design). ... constantly tweaking your circuits to get better performance, ... migrating a GPU to SOI is a walk in the park. ... CPU>> GPU ...
    (comp.sys.ibm.pc.hardware.chips)
  • Re: Charles Murray "The Plan" ends poverty
    ... The early days of electronic design automation are indeed interesting and if someone is going to write a history they had better hurry up. ... Donald Durr of RCA developed the first automated placement and wire routing program for LSI circuits in '65, ... I've had some experience with large systems in which the wrong circuit bounce in a switch or relay could set some relays to chatter and the system to wildly respond. ... Capacitors slowed down the switching, and helped the bouncing, but nowadays there are processors polling relays without debouncing circuits to determine whether they have switched. ...
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