Re: AMD to produce ATI GPUs in Dresden

In article <1154538214.449254.144600@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
dkanter@xxxxxxxxx says...
I don't have a bloody clue. IBM designs a lot of stuff, he could be
working on the z9 MPU, which is hardly aggressive implementation,

You havent' a clue.

Care to elaborate? Do you mean to tell us that IBM is using cutting
edge MPU design techniques to achieve high performance the Z900 and
other mainframe processors?

Why does IBM *have* high-end fab capability? Why would IBM use
less than "cutting-edge" design techniques on products with the
*HIGHEST* margins? Think about it. For a wannabe anal-yst, you
sure haven't studied the market much.

Mainframes are *not* in any way shape or form competitive based on
computational capabilities, as embodied by, say, SPECint/fp. They most
likely don't do well on TPC-C either.

Dunno about silly benchmarks, but the z's are used for some of the
largest transaction processing systems in the world. The're not
expensive because they're pretty.

However, they are some of the
most reliable systems, with a vastly superior IO architecture to most
of what exists. Oh yea, they also probably have the most (or second
most) valuable set of existing applications.

Now you're getting the idea.

If you wish to highlight innovative, bleeding edge architectural and
circuit techniques in the z9 systems, feel free. I certainly don't see
SMT being deployed in mainframes...at least for several years. I will
more than happily retract my statement if you can provide proof that
mainframes actually are aggressive architecturally and circuit wise.

Good grief. Do you really think SMT is that advanced? Come on,
it's a simple tweak (a friend was granted the important patents on
it long ago). Yes, every design trick known is put in the z's. It
wasn't until the mid '90s that they could use CMOS at all, and it
took a generation for CMOS to catch up even then. Before '95, give
or take a little, it was all ECL.

There's nothing wrong with not being on the cutting edge, and I'm sure
that quite a few IBM customers prefer to be on systems that are
designed in a relatively conservative fashion.

Clue up!

he
could be doing POWER6/6+, he could be working on contract design for
CELL or Xbox, he could be doing the X3/X4 northbridge.

Dunce, I said CPU.

Which eliminates one of the possibilities.

Maybe he worked on those older embedded cores that were sold to AMCC...

Maybe you're just intentionally being a jackass. Since you think my
CV matters so much, the last seven years have been PPC750->
Nintendo->a few more 750 variations->PPC970->PPC970MP->PPC970FX->
[codename deleted]. Before that, 6X86, 6X86MX, and once upon a
time 3090 and ES900 crypto. That covers the last 20 years or so,
need more?

A simple "I have worked on the PPC970 line" would have worked...

....a lot more than "I have worked on". Hell, I've worked on a
PDP11 too.

I've worked on both bulk and SOI projects (as well as bipolar),
both IBM and vendor microprocessors, logic design, analog,
verification, and who knows what else. ...and your experience is
exactly? Fill in the blank: -><-

My experience is with performance analysis, benchmarking,
microarchitectural analysis and statistical modelling.

Study more.

> I would agree that porting a GPU to SOI should be easier than
porting a
CPU, especially since *on average* you have less custom design work.
However, I think characterizing either as 'trivial' is silly.

The guys who have adopted SOI (IBM, AMD, Freescale, etc.) had their
major initial problems in getting the process for laying down circuits
on SOI right. Once that was taken care of, they now just use SOI like bulk.

Right, and they just ignore the FB effect or any of the other differences.

What an idiot. Of course you don't ignore FBE, you *USE* it.
...and the differences are invisible to the logic designer. Who
cares what the technology underneath is?

You seem to have missed the point of my comment.

Nope. It's irrelevant to the discussion. AMD already has a mature
SOI process. That's no longer a variable.

Or the crappy yields that Nvidia complained about...

Everyone has issues with yield now and then. I always though the
first go at a new line, new technicians, 90nm, and 300mm (and, and,
and,...) was a tad risky, but I'm not about to discuss the details
of dirty laundry. Everyone has PHBs too.

Fair enough, I wouldn't expect you to talk about sensitive things in a
public forum. My point is that you cannot simply *assume* that yields
will be good, based on results for relatively small full custom devices
that use a lot of SRAM, when talking about much larger semi-custom
devices that use very little SRAM.

Good grief! Yes you can. If it works for CPUs it *WILL* work for
GPUs. Even you say GPU << CPU.

You, on the other hand, have no problem criticizing what you've
never done and have no clue about, unless of course it's your pal
Intel. They can do no wrong.

Right...I don't seem to recall having ever said that.

Your alliance is as clear as Tom's.

I think Intel's
does quite a lot wrong, like going from being a near or actual
monopolist to letting an upstart competitor into the market. Or
pursuing the P4 design 2 process generations too far (ironically, the
POWER6 appears to be following in the P4's footsteps in terms of
pursuit of clockspeed). Or creating a culture that does not allow
outsiders to succeed...

Intel has bumbled around just as much as anyone else in the industry.
Everyone makes mistakes, IBM, HP, Dell, Sun, Intel, AMD, nobody is
immune. In fact, ISTR pointing that out and being fiercely opposed by
some folks who think AMD can do no wrong...

....except kick Intel's donkey, eh?

--
Keith
.

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