Re: AMD to produce ATI GPUs in Dresden
- From: "David Kanter" <dkanter@xxxxxxxxx>
- Date: 1 Aug 2006 11:09:56 -0700
Keith wrote:
In article <1154406777.178933.105860@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
dkanter@xxxxxxxxx says...
[snip]
I really wish you wouldn't snip attributions. It's a really bad
habit.
OK.
This "bad idea" has been done before.
When and where? Did they hit their release targets?
Were there any yield issues?
IBM. I'm not going to get into specifics.
So you won't say whether or not it turned out to be a horrible idea?
It works fine, within the parameters I've mentioned (mature SOI
process, working design). Bringing up SOI is a PITA; going back is
trivial.
I would expect that if they wanted to switch over
they would start with designs that haven't done much PD. My rough
estimate is that the design time for a GPU is 3 years, and PD probably
starts after 1 year. After they start PD, I don't think they'd
retarget.
Have you ever *done* this? Me thinks you're talking though your
hat, again.
No I haven't, I'm not an EE. If you have a timeline you'd like to
suggest, go ahead...
I already did. Less than a year, assuming a good design.
What constitutes a 'good design'?
No respins to fix bugs.
<snip>
I don't really buy this argument. Mainly because you are going to be
constantly tweaking your circuits to get better performance, lower
power or ideally both. That means you have to know what is going on in
circuit land...
Of course you don't buy into reality. Logic designers don't tweak
circuits. They select books the circuit designers have already
qualified. One doesn't go messing with circuits once the logic is
cast. Can you say "chase your tail"?
So what happens if your target frequency is say, 600MHz, and it turns
out you can only hit 400MHz, but you have 3-4 months before tape out?
Do you just sit on your ass and let the circuits moulder? Or do you,
perhaps, start tweaking things to get improvements, track down critical
paths and fix them?
If you're off that far, you're dead. It's time to shitcan the
entire design, fire all the architects, and sell flowers on the
street corner because you aren't cut out for this business. For
lesser "oopses" (happens all the time) the designer isolates a
critical path at a time then restructures the logic, picks faster
(higher power) "books", diddles with wiring geometry, reduces
loading, moves gates closer together, cheats, steals...
That sounds an awful lot more than 'pick a different book', it sounds
like 'pick the best book, and if you need more, start playing around'.
Or perhaps I'm walking away with the wrong impression.
Or do you perhaps go back to the logic guys and say: "Hey, you blew a
lot of timing on this one chunk, could we try something quicker..."
Yes, but unless it's an unmitigated disaster (fire the
architects...), you don't go back to the circuits guys; too late.
Logic is
logic, fer chrissake. The biggest problem with SOI is getting the
circuit designs right.
And yields...
Remember, AMD has a mature SOI process. The yield thing isn't part
of the equation.
I'm not really that sure. Acceptable yields for a 100mm^2 die may be
unreasonable for a 350mm^2 die, especially considering that GPUs have a
much higher density of logic, which is going to be more vulnerable to
defects. For a CPU, you at least have a pretty good chance of hitting
cache, which is easy to fix.
That's irrelevant to the issue at hand. I'm not letting the goal
posts move, this time.
I don't think that's moving the goal posts at all. AMD has a mature
process for SOI, with good yields for *THEIR* chips, which are all
relatively small and contain a lot of SRAM. GPUs are large and contain
little SRAM. Yield and design are both reasons why someone might opt
not to use SOI. Certainly, Nvidia was pissed about their yields from
IBM, which lead to them going straight back to TSMC.
They are both important aspects of the equation.
My experience is with CPUs, so calibrate from there. According to
your assumption, migrating a GPU to SOI is a walk in the park.
I think you're putting words in my mouth.
No, my experience is with CPUs.
Your assumption (which I don't really believe, but no shock there):
CPU >> GPU
My statement:
CPU PD can be turned (bulk -> SOI) in a year (fact)
Therefore:
A turning a GPU from bulk to SOI is a walk in the park.
I'm saying that generally CPUs are more complex than GPUs; certainly an
ARM7 isn't as complex as the most modern GPU, but...as a general rule
of thumb, a CPU is going to be more complex than a GPU.
We're not talking ARM. We're talking modern high-end widgets.
OK, thank you for clarifying. Was it really that hard?
I would agree that porting a GPU to SOI should be easier than porting a
CPU, especially since *on average* you have less custom design work.
However, I think characterizing either as 'trivial' is silly.
Three years is nuts.
Read what I write, not what you want to read. I said in my estimate a
GPU takes 3 years from start to finish, a CPU takes 5 years. I then
said "its likely they don't retarget once they start PD", which is
probably after 1 year. You have made a somewhat convincing argument
that retargeting for SOI is not a huge issue if you have the experience
lying around. You have yet to make an argument that designing a GPU
takes less than 3 years.
If you are saying you can port a SCSI controller from bulk to SOI in a
year, then I'm not sure that means much. I'm hoping you are talking
about a substantial design...
Now really, a SCSI controller in SOI would be rather silly, no?
Sure, but I don't know what kind of design you were working on, and you
haven't chosen to share that information. Therefore, I can't really
come to any conclusions about whether your experience porting is
closely correlated to that of a GPU, a lower bound, an upper bound,
etc...
I told you, my experience is with CPUs.
There's a wide range of CPUs that were designed at IBM. There's the
older stuff that was sold to AMCC, there's the POWER4/5/6, there's the
CELL MPU, the Xbox MPU, the z9, etc. etc. and there are probably others
I didn't mention because I wasn't aware of it.
DK
.
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