Re: AMD to build 3rth factury in Dresden Germany

On Tue, 30 May 2006 09:39:09 GMT, Jan Panteltje <pNaonStpealmtje@xxxxxxxxx>
wrote:

On a sunny day (29 May 2006 20:04:03 -0700) it happened "YKhan"
<yjkhan@xxxxxxxxx> wrote in
<1148958243.289266.154360@xxxxxxxxxxxxxxxxxxxxxxxxxxx>:

Jan Panteltje wrote:
On a sunny day (Mon, 29 May 2006 12:52:54 -0400) it happened Yousuf Khan
<bbbl67@xxxxxxxxx> wrote in <EIqdnVg4Nd51u-bZRVn_vA@xxxxxxxxxxxx>:

Jan Panteltje wrote:
That says 45000 wafers per month, so say half a million each year.
How many processors on average on a wafer?

Assuming 150 mm^2 dies on average, that would be about 450 dies per
wafer. That goes upto 650 dies, if the average is 100 mm^2.

so 500 x 1/2 million = 250 million processors / year.
Now that is a respectable number.

I can't see AMD going under 150 mm^2 even at 65nm, considering that
quad-core is on its way. However, if they adopt a ZRAM L3 cache, they
might be able to pull it off.

Yousuf Khan


ZRAM, now I decided to look that up in google, and found this:
http://www.geek.com/news/geeknews/2006Jan/gee20060124034376.htm

Anyways, we see so much new tech, how long would it take to test
that, so one would be sure it would work... maybe not so long indeed,
no new materials involved, it is an old effect.

It's been shown to work:
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=174910622
http://www.eet.com/showArticle.jhtml?articleID=59302249
http://www.reed-electronics.com/electronicnews/article/CA6260580

128Mb at 90nm even in a prototype chip would seem to be good evidence of
viability but the 3-years mentioned by Toshiba to go "live" possibly also
indicates some kinda problems.. maybe with process "integration"? I guess
we'll see what AMD/IBM makes of it

IIRC the VC activity for ISI is linked up with the Soitec "arrangements"
which could also indicate taking a pinch of salt with the good news. Note
also the founder of Soitec died recently - hope he didn't take anything
with him!:-)

Yes and a larger cache may give AMD even more speed advantage...
Wait and see I suppose...

AMD's talk has been of an L3 cache - ain't gonna cut the mustard against
the 4MB of L2 shared cache on Intel's Core2 chips IMO. In fact AMD's dual
core design with the X-Bar does not seem to lend itself to a shared cache
implementation.:-(

--
Rgds, George Macdonald
.

Relevant Pages

  • Re: What is the maximum useful size of a CPU die?
    ... Smaller dies result in more dies per ... wafer and with X defects per wafer you'll end up with more working ... Its quite common to break units within a chip into various clock ... runs at a lower frequency than the center of the out-of-order engine. ...
    (comp.arch)
  • Re: LT1037 packages
    ... > interpret the data sheet I see the differences are there, ... I guess there is one process, then the dies on the wafer are tested, ...
    (sci.electronics.design)
  • Re: What is the maximum useful size of a CPU die?
    ... Smaller dies result in more dies per ... wafer and with X defects per wafer you'll end up with more working ... I am not aware of many designs that were limited by the reticle size rather than economic constraints as pointed out. ...
    (comp.arch)
  • Re: AMD to build 3rth factury in Dresden Germany
    ... How many processors on average on a wafer? ... Assuming 150 mm^2 dies on average, that would be about 450 dies per ... ZRAM, now I decided to look that up in google, and found this: ... Yes and a larger cache may give AMD even more speed advantage... ...
    (comp.sys.ibm.pc.hardware.chips)