Re: Intel introduces "Core 2 Duo"
- From: krw <krw@xxxxxxxxxx>
- Date: Fri, 12 May 2006 22:06:09 -0400
In article <4ck3ibF166lboU1@xxxxxxxxxxxxxx>,
cecchinospam@xxxxxxxxxx says...
NoNoBadDog! wrote:
Chris;
See my responses in line to yours...
"chrisv" <chrisv@xxxxxxxxxxxxxx> wrote in message
news:470962pvichilu5pl1fkgom3t6vpdrvtu1@xxxxxxxxxx
NoNoBadDog! wrote:
"chrisv" <chrisv@xxxxxxxxxxxxxx> wrote:
Some people think Conroe *might* compete-with, and
*might* even out-perform, AMD's best. I for one will not be surprised
if it does - it's an all-new design and it will initially have the
advantage of being on a .065 process.
Doesn't matter how fast the core will be...it will still be tied to a
measly
533MHz FSB,
533MHz DDR is "measly"? Whatever...
When AMD runs at 2GHz, then *YES* 533 MHz is very measly.
But the amd ht is 2 bytes in each direction. how many bytes is the 533?
In how many directions (we're really talking about a four byte
interface, with no turn-around).
has no on-die memory controller,
Okay, one true disadvantage.
small handicap
Latency isn't "small" to processor types. ...x86 in particular
since it's so register poor thus is load-store dependent (something
not brought up by the OP).
the two cores cannot
communicate directly, but consume clock cycles communicating through the
L2
cache, taking the L2 cache away from doing its real job, has no
hypertransport bus....I could go on, but you get the picture.
Not that any of that impacts performance all that much...
It results in at least a 50% drop in availability of the L2 to do its
primary job..caching data. That is why they plan to double it from 2 to 4
MB. But it is still relatively inefficient and adding more cache does not
compensate for the loss of clock cycles from haveing to communicate through
the L2 as opposed to direct communications.
What direct communication?
Each processor owns its own memory. Throw on a touch of processor
affinity (a done deal) and AMD's architecture is a winner.
What is architected in X86 for "direct
communication"? It all takes place via memory near as I can tell. So
if you don't share L2 you have to go to dram?
Architected in x86? That's not an architecture issue, rather
implementation. AMD has it all over Intel here.
If Intel really has re-prioritized x86, then there is no reason it won'tIntel may be updating its chips, but they are still being deployed on 10
year old motherboard designs.
Not a single new motherboard (other than chipset and connectors) has been
introduced. You need to do your homework before correcting someone else,
particularly when you are wrong and the one you are correcting is right.
Not true. Your hyperbole does not further your cause.
(snip)
Can I watch you eat crow this fall if/when Intel takes-back the
performance lead?
I have always posted that I will acknowledge it is Intel gains the lead. I
used to be dedicated to Intel. But you and I both know that Intel is not
known for changing it's ways. I fully anticipate Conroe and Merom to be on
par with AMD, but it should have happened two years ago. AMD will continue
to innovate, and Intel will continue to obfuscate (a new sticker...a new
numbering system...yada yada yada...)
Bobby
be competitive in power and performance within a few years of the
redirection. It is not as if they don't have good processes or know how
to do chip design.
I agree, sorta. Have they given up on Itanic though? I haven't
seen any evidence that they're in this (x86/64) for the long haul.
It doesn't fit their profile.
Newsgroups trimmed
Simply killfile the ones you don't want to follow. ...no need to
advertise your preferences.
--
Keith
.
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