Re: Athlon 64's: a shared memory bus?

On Thu, 02 Mar 2006 16:03:40 GMT, "pigdos" <NA@xxxxxxxxxxx> wrote:

This is all I wanted to hear. Why George felt the need to denigrate me at
every turn I'll never know. I didn't know this, that's why I asked.

What do you expect? You asked. You got correct answers. You argued...
from a position of complete ignorance. You refused to look at docs which
were referenced. Umm, you denigrated yourself.Ô_ô

Does PCIe feature any functionality equivalent to AGP w.r.t. storing texture
data in system memory?

If you would read your beloved AGP 3.0 specs you'd know that it no longer
refers to DiME (or "execute mode") for texture data. This is at least in
part because AGP 3.0 added support for isochronous transfers, a more
generic form of high speed guaranteed "packet" response for data transfers;
this was essentially to cope with the demands of new devices which do
streaming and video capture. PCI-e docs are not publicly available but I
believe it also supports isochronous transfers. Perhaps someone who has
access to the docs can comment... but there are certainly several PCI-e
video cards which use UMA and partial UMA for *any* video data. As for
DiME I don't believe it was used by any major game software for texturing.

--
Doug
"Tony Hill" <hilla_nospam_20@xxxxxxxx> wrote in message
news:16o7025ftf9gea6he3fih8hdbgolqli3d6@xxxxxxxxxx
On Mon, 27 Feb 2006 03:17:17 GMT, "pigdos" <NA@xxxxxxxxxxx> wrote:


Err, not really... but for the sake of argument we'll assume that
there's some accuracy to that statement. So, umm.. what's your point
here? There's nothing too different about how the Athlon64's memory
controller reads/writes to memory as compared to that of a P4 system,
it's just that the controller has been moved from the Memory
Controller Hub (MCH) onto the CPU die itself.

If this doesn't involve two separate buses
then we still have to turn-around the bus before we can even write
this data or read more. How wide is the data path between the A64 and the
BIU (it might not be a north bridge, but it sure as hell is a BIU of some
type)? For AGP writes this might not be an issue, but for AGP reads it
might.

Hypertransport IS two separate buses. Hypertransport is a
unidirectional point-to-point I/O connection. In the case of the
Athlon64/Opteron the two directions are both 16-bits wide and run at
either 1600MT/s or 2000MT/s (800 or 1000MHz DDR, depending on the
stepping of the processor and chipset).

It's neither an issue for AGP reads or writes.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca



--
Rgds, George Macdonald
.

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