Re: Athlon 64's: a shared memory bus?

On Mon, 27 Feb 2006 02:50:13 +0000, pigdos wrote:

"Properly," according to whom?

Everyone else in the civilized Usenet. Only self-centered kidz top-post.

I was using usenet before

For what, toilet paper?

there were any such standards.

Show me convincing evidence as to WHY top-posting is so evil.

What is so hard to understand about writing for the reader?

Net nazi.

Net loon.

Where anywhere in the AGP 2.0 spec does it mention DMA mode?

Do you have any clue what you're talking about?

No where. Neither do any chipset datasheets I have. Cite your source
please.

George already did, nutcase. If it walks like a duck...

Then I'll be more specific, whatever chip that has taken over the
functions of the north bridge w.r.t. AGP/PCI xfers.

Who knows what the hell you're talking about, since you top-post. Loon!

I was never arguing that CPU<--->memory xfers were any worse, I was
arguing that AGP memory xfers (DIME?) could be slower. I'd like to see
some proof that A64's have dedicated hardware for the AGP GART TLB as
well, because I doubt it and I couldn't find any mention of such
hardware in the datasheets I've read for the A64.

YOu don't get it. CPU performance is about, umm, CPU performance. Who
cares about AGP performance since graphics cards have more memory on them
than one cares about. BTW, that's always been the case. AGP has always
been a solution looking for its problem.

If you were a Phd in EE I'd take your word as fact, since you're not, I
don't...

No PhD, here, only 30+ years in the biz. If you need to listen to a PhD
to move you ass, you won't get squat done.

--
Keith
.

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