Re: PCI Burst transfers initiated by the Northbridge

On Tue, 22 Nov 2005 16:30:06 GMT, "Alexander Grigoriev" <alegr@xxxxxxxxxxxxx>
wrote:
>
>"daytripper" <day_trippr@xxxxxxxxxxxxxxx> wrote in message
>news:jn65o1l0n66atjp3q884for5r1uae2658u@xxxxxxxxxx
>> On Tue, 22 Nov 2005 03:47:20 GMT, "Alexander Grigoriev"
>> <alegr@xxxxxxxxxxxxx>
>> wrote:
>>>
>>>A company I user to work for, had a PCI communication ASIC designed. For
>>>some reasons, the PCI interface was not done right and would lock up if a
>>>memory write burst was initiated by CPU bridge. And we took pains to make
>>>sure we NEVER write to successive registers, otherwise burst occured and
>>>the
>>>system was screwed.
>>
>> Shades of the early days of PCI, when erratum flew like confetti, and bios
>> and
>> driver writers held chip designers hostage...
>>
>> And yet another good reason not to use host-initiated bus transactions of
>> any stripe: Writes to memory mapped PCI space are *allowed* to be coalesced by
>> the host bridge. If the ASIC designers fail to implement their target state
>> machine to handle the resulting "burst" of register writes correctly to
>> begin with, the driver must utilize barrier instructions to get the write buffer
>> flushed between "register" writes, a pitiful way to run an airline...
>>
>> /daytripper
>
>You confuse write-combine and write burst.

Nope. I don't recall any bounds being placed on the definition of "burst" to
this point...Combining is synonymous with coalescing, and leads to a
multi-dataphase write transaction, which by any common definition is in fact
seen as a "burst" of data by the target agent...

/daytripper
.

Relevant Pages

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