Re: Intel cancels next-generation Xeon for even-more-next-generation Xeon

On 27 Oct 2005 20:59:09 -0700, "David Kanter" <dkanter@xxxxxxxxx> wrote:

>> Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express.
>> That was in a futile attempt to derail any momentum building for AMD's
>> Hypertransport. Of course PCI-E is no competition for HT, it's much too
>> bloated to be a chip-to-chip interconnect. AMD never fell for it, and
>> kept HT as simple as possible while Intel threw as much bling-bling
>> into PCI-e to dazzle people with features.
>
>How is it bloated, oh font of interconnect wisdom? Perhaps you don't
>realize it, but serial interconnects are far higher bandwidth...
>
>> Now it looks like AMD might even use PCI-e against Intel, if the
>> rumours about AMD building a PCI-e link directly into its processors
>> can be believed.
>
>I don't see how that is "using PCI-e against Intel"...
>
>> > And not long ago I read somewhere Intel was going to use a dual bus like
>> > the one AMD used on the Athlon MP, I can only hope that was false or
>> > they have now dumped that too, I doubt it would get them far, still a
>> > shared bus right?
>>
>> Yeah, I think that was supposed to be in the Deerfield processor that
>> Intel just cancelled.
>
>No it's not cancelled moron. Deerfield is a LV IPF part. They
>cancelled Whitefield. White, not deer.
>
>Intel's next gen server chipset is a wonderful piece of work and
>features dual independent FSBs.

'Cept they're a trifle late to the party - IBM's already done it.

> I suspect the next generation after
>that will feature 4 or more.

If you'd been paying attention, it'd be clear that the "next generation"
will be no more FSB - it won't exist, it'll be kaput, it'll be an err,
ex-FSB. The only reason that Intel is not going to an intergrated memory
controller sooner is because of the mess of market segmentation they've
attempted to create - IOW the marketing tail has been wagging the technical
dog for far too long.

In fact *I* suspect that the just cancelled chip was to be the last FSB CPU
- IOW the road-map adjustment which brings a later development forward to
replace it is the first integrated memory controller CPU. Untangling
marketing bungles, rearranging road-maps which are falling apart under
competitive pressures, does take some time and umm, energy.

--
Rgds, George Macdonald
.

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