Re: Intel cancels next-generation Xeon for even-more-next-generation Xeon

David Kanter wrote: 
Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express.
That was in a futile attempt to derail any momentum building for AMD's
Hypertransport. Of course PCI-E is no competition for HT, it's much too
bloated to be a chip-to-chip interconnect. AMD never fell for it, and
kept HT as simple as possible while Intel threw as much bling-bling
into PCI-e to dazzle people with features.



How is it bloated, oh font of interconnect wisdom?  Perhaps you don't
realize it, but serial interconnects are far higher bandwidth...


Now it looks like AMD might even use PCI-e against Intel, if the
rumours about AMD building a PCI-e link directly into its processors
can be believed.



I don't see how that is "using PCI-e against Intel"...


And not long ago I read somewhere Intel was going to use a dual bus like
the one AMD used on the Athlon MP, I can only hope that was false or
they have now dumped that too, I doubt it would get them far, still a
shared bus right?


Yeah, I think that was supposed to be in the Deerfield processor that
Intel just cancelled.



No it's not cancelled moron.  Deerfield is a LV IPF part.  They
cancelled Whitefield.  White, not deer.

Intel's next gen server chipset is a wonderful piece of work and
features dual independent FSBs.  I suspect the next generation after
that will feature 4 or more.

David


Dual FSB on the chipset. Those guys must be geniuses. (ever look at summit?)

del

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions, strategies or opinions.”
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