Re: AMD CPUs in ASRock motherboards

On Wed, 26 Oct 2005 13:45:12 +0200, Kai Harrekilde-Petersen
<khp@xxxxxxxxxxxxx> wrote:

>George Macdonald <fammacd=!SPAM^nothanks@xxxxxxxxxxxxx> writes:
>
>> BTW Robert seemed to suggest a cache line of 128-Bytes but on both Intel &
>> AMD systems the maximum burst is 64-Bytes, i.e. 4-beat burst on dual
>> channel systems. The P4 L2 cache line *is* 128Bytes but each line is two
>> sectors of 64Bytes.
>
>>From personal experience with PCI read bursts vs a P6 bus, I was under
>the impression that 128 bytes was "the thing". We saw a huge
>degradation in performance because our PCI chip only read 64 bytes at
>a time*, and the P6 memory controller would prefetch 128 bytes, discard
>the latter 64 when the burst stopped, and then re-fetch the same damn
>128 bytes when we came back for the next 64 byttes on the PCI bus.

Well I can't argue with empirical evidence,:-) but which chipset was that?
When I wrote the above, I'd only looked at i875's data*** in detail; on a
look at i925x, I'm confused: it's contradictory on 8-beat vs. 4-beat for
dual channel interleaved. I guess there's nothing like practical
experience but I'd still like to see Intel's docs cover it.

--
Rgds, George Macdonald
.

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