Re: AMD CPUs in ASRock motherboards

George Macdonald <fammacd=!SPAM^nothanks@xxxxxxxxxxxxx> writes:

> BTW Robert seemed to suggest a cache line of 128-Bytes but on both Intel &
> AMD systems the maximum burst is 64-Bytes, i.e. 4-beat burst on dual
> channel systems. The P4 L2 cache line *is* 128Bytes but each line is two
> sectors of 64Bytes.

>From personal experience with PCI read bursts vs a P6 bus, I was under
the impression that 128 bytes was "the thing". We saw a huge
degradation in performance because our PCI chip only read 64 bytes at
a time*, and the P6 memory controller would prefetch 128 bytes, discard
the latter 64 when the burst stopped, and then re-fetch the same damn
128 bytes when we came back for the next 64 byttes on the PCI bus.


*) It was a PCI-SCI bridge chip, so all internal buffers were designed
for 64 bytes bursts, as this fitted into the 64-byte packets on
SCI. In a later spin, we changed the internal buffer handling to use
128 bytes at a time on PCI, and then schedule 2 64-byte packets on SCI
for each buffer.

Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
.

Relevant Pages

  • Re: AMD CPUs in ASRock motherboards
    ... >>>From personal experience with PCI read bursts vs a P6 bus, ... >>128 bytes when we came back for the next 64 byttes on the PCI bus. ... > Well I can't argue with empirical evidence,:-) but which chipset was that? ... bursts, but my memory on that is failing me. ...
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  • Re: AMD CPUs in ASRock motherboards
    ... >>From personal experience with PCI read bursts vs a P6 bus, ... >128 bytes when we came back for the next 64 byttes on the PCI bus. ...
    (comp.sys.ibm.pc.hardware.chips)
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