Re: SPI on the User Port ... Mode Hang-Ups.

On Jan 28, 5:59 pm, Jim Brain <br...@xxxxxxxxxx> wrote:
BruceMcF wrote:

CIA native is the second clock line (clock=1) and the second phase
line (phase=1) ... mode %11 = ... Mode3.

And, I'll show your idea in CLK line 3 below.

> \_________________________________/--
> __/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\____
> --\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/----
> ____/-\_/-\_/-\_/-\_/-\_/-\_/-\_/--\_
> .=1=x=2=x=3=x=4=x=5=x=6=x=7=x=8=x=...
> ..x=1=x=2=x=3=x=4=x=5=x=6=x=7=x=8=...

CLKout=SS XOR CLK gets close to what you want, using no select lines

SS CLK CLKout
1 1 0
0 0 0
0 1 1
1 0 1

If you put a F/F in there that clocked /SS out on falling edge of CLK,
that would take care of the beginning. The end would need something to
override that (maybe use /CLR on a F/F to reset it. Thus:

PORTD:4 is sent to D of F/F
/Q is sent out as SSout
CLK of F/F is hooked to CLK
PORTD:4 is sent to /CLR
CLKout is SSout XOR CLK

SSout can be use as input to '138 to give 8 (or 16) targets, as noted
before. PORTD:4-0 is hooked to 138.

Thus, any address between 16-31 will select a device.

It would require 3 ICs ('138, '86 and some D F/F with CLR ('74?)

Jim

Very close ... to be safest, clock should probably already be low when
SS is pulled high ... I was thinking that it would be somewhere along
the line of:

SS from one PortB line directly. A second PortB line, Clock Select,
and two STATEs (as far as I understand, each of the eight GP I/0 in a
PEEL18CV8 can hold state), and

SCLK = CSL & CNT & STATE1
STATE1 = CSL & ( STATE2 | /CNT )
STATE2 = CSL & (STATE1 | /CNT )

I don't know if that works, but the idea for the protocol is:

(1) pulling CSL low when SS is high resets the two states.
(2) CSL is pulled high, while SS is still high, priming the latch
(3) The states are held low as /CNT is low, so SCLK is low
(4) When CNT drops, the states pull up ... and SCLK=CNT is still low
(5) Valid data is now available on both MISO and MOSI
(6) When CNT rises, SCLK rises, and the states are latched high

(7) When the last byte is read and/or written, pull CSL low
* states are pulled low
* the SCLK drops

(8) then pull up SS

And to switch from Mode0 to Mode3, simply leave SS high, pull CSL
high, and write a dummy byte out. Busy loop, do something else, or
interupt when the dummy byte is out, and leave CSL high while pulling
SS low ... both states are high and the clock is passed through.

I may not understand how smart the GP I/O latch is in a PEEL18CV8, ...
but learning how to use fifteen year old technology to connect twenty
five year old technology to five year old technology would, of course,
be part of the charm.
.