SPI on the User Port ... Mode Hang-Ups.

OK, the User Port has two serial shift registers, as well as all of
PortB from one of the CIA's. Plus one generic I/O line from PortA and
the Handshake line.

The SPI interface is a four wire synchronous interface, and is a "de
facto" interface rather than a standardised-then-spread interface. The
controller is called the "Master", and the device being controlled is
called the "Slave". I normally call it the "Device".

SCLK: the serial clock
SS: Device Select. Pulled LOW to select the device.
MOSI: Serial Master Out Device In line ... output from controller to
device.
MISO: Serial Master In Device Out line ... input to controller from
device.

As a de facto standard, much depends on the specific device ... most
SPI devices are byte-wide, but some are 16-bits wide, and some Digital/
Analog chips are 12 bits wide.

One thing that makes SPI popular is that in the device being
controlled, the interface is often little more than a serial shift
register with bi-directional parallel access inside the device, and a
counter to trigger a write of data to the shift register and/or read
data from the shift register.

One of the most ubiquitous SPI interfaces was introduced with the
Playstation One, where digital switches were replaced with an joypad
controller interface that was read from over an SPI line. Other SPI
devices include a very large selection of flash RAM ... SPI is one of
the common bootflash interfaces, since the clock can be as fast as
both sides can handle ... SD and MMC cards, which support SPI as well
as their native three wire serial interface, and MAX parts that
provide both USB host controller and serial UART.

What I didn't understand, until I recently read through an example of
implementing an MMC interface for a 6502 hobbyist computer, is that
there are four possible modes implied by the above, and as a de facto
standard, all four modes have been used in one SPI device or another:

* The serial clock can start high, with the leading edge being the
falling edge and the trailing edge being the rising edge, or start
low, leading with a rise and trailing with a fall
* The data can either be available/read on the leading clock edge or
trailing clock edge.

If the User port is set up with the CIA serial shift register running
flat out, and the clock line for the register chosen as MISO tied to
the clock line for the register chosen as MOSI, it is a high clock,
trailing edge SPI ... this is called "Mode 3". Then the SS line can be
either the sole general purpose PortA I/O pin, or one of the eight
PortB I/O pins.

As C64 I/O goes, its reasonably nippy. The fastest the CIA can be
programmed to go is one serial shift register cycle for each 4 clock
cycles, so that is one byte transferred per 32 clock cycles. If the
next byte is loaded before the 32 clocks are up, its continuous
transfer, so that's 1 million cycles divided by 32 or 30KB/s+

The Mode 3 is intrinsically the "native" mode when using a CIA ... the
serial shift data is available from the end of the falling edge of the
clock cycle, through the following rising edge, and to the start of
the next falling edge.

The most common mode is Mode 0 ... data is available and required when
the clock cycle starts, and the clock starts low, rising and falling
for one complete clock cycle.

What can you do to get Mode 0 from the CIA? Well, one solution is to
bit bang. That is, specify SCLK, SS, MOSI and MISO at PortB pins and
just do it in software. Getting a byte out that way takes around 300
to 350 clocks, or about 3KB/s ... a program taking logging data from a
a 9600bps serial port would be able to keep up, but only if it did not
spend a lot of other clock cycles doing anything interesting.

However, Mode 0 and Mode 3 have their data available in the same SHAPE
of the clock cycle ... low, rising, and high ... its just a different
PHASE of the clock cycle, depending on whether the clock starts low
and that is the start, or the clock starts high and that is the end.

So hardware support would be able to convert the "intrinsic" UserPort
SPI into a Mode 0 SPI, if it could hold the serial clock low when the
serial bus was idle, keep it low until the first rising clock of the
hardware CLK line, and then when all the work for that transfer is
finished (one byte or hundreds of bytes), pull the clock low again
before deselecting the device.

Working that through, back of the envelope style, it turns out that
that is much easier to do in hardware if you give the hardware extra
help by having two "mode" lines ... the device select line, which is
pulled low at the start of the process and pulled high when the
process is over, and a phase line, which is flipped one way to to put
the hardware into "hold low until rising edge, then follow the clock"
mode, and flipped the other way to actually do the final pull down of
the serial clock line, after the CIA hardware clock is finished.

To me that says, eight PortB lines are four pairs of select and mode
control lines, for four possible devices on the SPI backplane. Since
that gives internal flash RAM ... say, 512KBytes, (described in parts
catalogues as 4Mbits), an SD/MMC socket, a high speed RS-232 UART, and
an option of a USB host controller, four seems ample. If it was me,
and given that some form of CPLD (maybe a PEEL18CV8) is required
anyway, I'd have design it with the internal flash and the UART, and
the other two SPI ports as DB-9 connectors on a specified pin-set
(female DB-9 connectors to avoid the RS-232 being plugged into the
wrong connector).

.

Relevant Pages

  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... I don't consider my SPI code as finished but I've seen what ... of the SPI clock at the master where it *should* be for a normal SPI system. ... But does this choice force me to, for example, clock the CPU ... this clock frequency does not need to be used when communicating ...
    (comp.lang.vhdl)
  • Re: Antii, can you give us an update?
    ... But there can be additional transitions ... being slave SPI in FPGA, where external MCU is SPI master at about 4 ... this secondary SPI is where i did see the shift register to fail (when ... it uses local routing), but now it is forced global clock, and besides ...
    (comp.arch.fpga)
  • Re: Mixed clocked/combinatorial coding styles (another thread)
    ... I don't consider my SPI code as finished but I've seen what ... of the SPI clock at the master where it *should* be for a normal SPI system. ... But does this choice force me to, for example, clock the CPU ... If that's not your case, then you've got a wimpy CPU, but in that situation you wouldn't have a clock divider, and the data handling would be done differently. ...
    (comp.lang.vhdl)
  • Re: SPI unterminated
    ... the plan is to run the SPI signal ... I would put a series resistor at the clock driver (there is ... You may want to put ground pins adjacent to the clock pin to ... But if you would rather be safe than sorry, or if the signals are going ...
    (sci.electronics.design)
  • Re: Augh! WTF megabaud?
    ... >worried about clock rate, bitbanging. ... dedicated SPI interface in the 68332 to program a couple of Xilinx ... chips (essentially SPI in slave serial mode) or whether to just keep ... We're planning a product with maybe 10 mbits of Xilinx configuration ...
    (sci.electronics.basics)