Re: IEEE-488 bus

On Jan 13, 1:05 am, Jim Brain <br...@xxxxxxxxxx> wrote:
christianlott1 wrote:
How difficult would it be to modify a 1541 and C64 to make this
change? I know about a lot of sw mods to speed disk access, but no hw
that uses mods on both C64 and 1541 to improve disk speed.

The 64 would be easy to mod (There was an article in an old C=Hacking
that allowed you to use the burst mode on the 64 with a 1571/81. The
1541 would have required a CIA to be installed, as CBM never did fix the
VIA bug. WDC's new VIA has the bug fixed, so you could theoretically
rpelace the 1541 VIA with a WDC 65C22S, and reroute the fast serial line
(then called SRQ) to the appropriate shift register on the VIA.

ga! really??

Pasi's article in C=hacking 19. ok.

Even with the 1541 mod, this doesn't seem like it would break
compatibility for software that don't use custom fastloaders? (yeah,
that's a question...)



I know it's the art of programming the 64 to count these cycles but
wouldn't it be a piece of cake to manufacture a C64 motherboard with
three separate busses so they didn't have to wait for each other?

Today, if you used dual port RAM, you could have no wait states on the
RAM (except during collision), but such things were not available at
economical prices then.


Creating a motherboard with such features with sockets for the CIAs,
6510, VIC2, SID etc.. This would doubtlessly be very expensive?
(another question..)



There must be some kind of 3-layer ram write through technology that
would allow the chips to independently view the same memory data on
their three independent ram chips?

It could have been developed then, but it would have required quite a
bit more engineering, and drove the cost up. Remember, we're talking
about a company that mandated the VIC have 1k RAM chips because they had
surplus. (And a company that decided when the 116 was ready for design
lockdown when Jack wandered by, looked at the mobo, and decided there
were few enough ICs on the board).

That's pretty funny :)
.

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