Re: 6502 microcode / pla equations

Thanks very much Allan,

What you described is exactly what I was searching for. Of course I
would still like to have a look at a readable schematic that is not
outdated or even wrong. Too bad a complete and correct schematic
doesn't seem to exist ...

So what you think is that if I stick to Adam Vardy's document then I
would be as close to the original implementation as possible ? Do you
know of any existing VHDL or VERILOG core that takes into account
Adam's documentation ?


On Tue, 24 Apr 2007 17:45:06 -0700, Allan <ajfengr@xxxxxxxxx> wrote:

Yes, there certainly is a PLA inside the chip. I don't believe
its contents have ever been published. I have access to the
schematics and have decoded the information. I'm presently looking
into those "illegal" instructions much as you are now.
From what I've seen, I can say the following:

1) Adam Vardy's document is very accurate and complete. Based on my
own analysis compared to his, the only discrepancies I can find are
for instructions which he also indicates are "suspect" or

2) Even with the instruction decoder PLA in hand, a lot of things are
vague or bewildering without intimate knowledge of the rest of the
schematic. Consider a few things I've found:

a) The "ROR bug" which was in the original 6502 is STILL in
schematics that were in use at MOS Technologies years later. It seems
somebody fixed the chip layout, but didn't update documentation for
b) Other bugs are still in the schematics which clearly were never in
the finished chip. For example, ROL and ASL instructions would seem
to be broken. Obviously they are not, so I had to cook up a fix of my
own for the schematic.
c) There are two product terms numbered "58", and both of these are
coded the same way. However they have different comments, indicating
they have different uses in the chip. Sure enough, the chip won't
work as the schematic indicates. I found and fixed one of the "58"
terms so I could continue my analysis.
d) A majority of the "illegal" opcodes depend on predictable behavior
when two registers or busses are shorted together (a logical "and" in
NMOS technology) So you have to consider that possibility.
e) Conditional branches are handled outside the normal instruction
logic, to keep the cycle count at an absolute minimum for the three

Best regards,

On Sat, 12 Aug 2006 00:34:17 +0200, Kroko <Krokodil@xxxxxxx> wrote:

Thanks for your reply. I know there are several free 6502 cores,
like T65 which is even cycle exact. All cores try to reconstruct
how the 6502 is working. All cores are mor or less compatible and
work is still in progress.

I wanted to know if the original architecture was ever published. I
mean how everything worked on the gate level, or how the PLA that
is decoding the opcodes inside the 6502 was working. I am interested
to see how the illegal opcodes result from the inner architecture of
the original 6502.

There are no "PLA equations" for the 6502 - it is a complete
CPU inside with internal state. There is a VHDL core on if that helps you.


Kroko wrote:
Have the PLA equations of the 6502 ever been published ?
I mean the equations that create the control signals for the
registers etc.. inside the 6502 core by decoding the fetched
opcode ...