Re: AT91R40008 Exception Handling
- From: "pod" <marcus.d.pollard@xxxxxxxxxxxxxx>
- Date: 14 Mar 2007 07:59:26 -0700
On 14 Mar, 14:39, "Not Really Me"
<scott@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
"pod" <marcus.d.poll...@xxxxxxxxxxxxxx> wrote in message
news:1173876193.985192.318020@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi,
I want to be able to have my own exception handler routine when ever
the processor enters either
UNDEF HANDLER
DABT HANDLER
PABT HANDLER
The processor has been remapped, and whenever the processor enters an
exception, it just sits there in its infinite loop. I want to be able
to have a routine that can handle the exception.
Any ideas ?
many thanks.
Marcus.
You should only need to have the vector branch through an indirect table.
Many startup.s files come set up with the table, but all the entries go to a
simple loop as you describe.
This is an example from another Atmel processor:
;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addressing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite
loop.
;- To ensure if a exception occurs before start application to infinite
loop.
;------------------------------------------------------------------------------
B InitReset ; Reset handler
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
B irqvec ; IRQ
fiqvec
B fiqvec ; FIQ
You should replace it with something like the following. In this example
all the vectors cause a branch to labels which initially are to the same
place. Write you own handlers and move the individual labels to the
appropriate routines. If your code is executing from RAM then you can fill
the table locations dynamically after startup. The [pc, #24] is a relative
reference to the address table. The VIC and FIQ are set to an offset of 20
because there is no entry for the reserved vector.
_start
; This is the location of the required interrupt
; vectors that are used by the arm core to handle
; system faults. The interrupts are esscentially
; handled out of a table. This is done so that if
; this code is moved to RAM, the actual address of
; an interrupt handler can be inserted into the table.
LDR pc, [pc, #24] ; Reset
LDR pc, [pc, #24] ; 0x04 - undefined instruction
LDR pc, [pc, #24] ; 0x08 - software interrupt
LDR pc, [pc, #24] ; 0x0C - prefetch abort
LDR pc, [pc, #24] ; 0x10 - data abort
NOP ; reserved vector
LDR pc, [pc, #20] ; 0x18 VIC IRQ
LDR pc, [pc, #20] ; 0x1C FIQ IRQ
; Exception vector table
;
; Table contains the addresses of the exception handlers. If this code
; is moved to RAM, then these locations can be updated to contain the
; addresses of real exception handlers. For parts which
; don't interface to SDRAM and code will probably run out of flash)
; substitute the (global) exception handler names into the table.
vec_reset_handler DCD __reset_handler
vec_undef_handler DCD __undef_handler
vec_swi_handler DCD __swi_handler
vec_prefetch_handler DCD __prefetch_handler
vec_abort_handler DCD __abort_handler
vec_irq_handler DCD __irq_handler
vec_fiq_handler DCD __fiq_handler
__undef_handler
__swi_handler
__prefetch_handler
__abort_handler
__irq_handler
__fiq_handler
default_handler
; All exceptions are handled by a default handler for now.
; The user or operating system can add functionality at
; run time if they wish.
; Note: To install handlers at a later time requires that
; the system have volatile memory mapped to 0. This can be
; accomplished via the remap register.
B default_handler
Scott- Hide quoted text -
- Show quoted text -
Hi scott,
thanks for your reply...
below is an excert of the code I am working with...
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0xF20] ; Vector from AIC_IVR
; LDR PC, FIQ_Addr
LDR PC, [PC, #-0xF20] ; Vector from AIC_FVR
Reset_Addr DCD Soft_Reset
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved
Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Soft_Reset B Soft_Reset
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
So, what you are suggesting is something like :
Vectors LDR PC, [pc, #24]
LDR PC, [pc, #24]
LDR PC, [pc, #24]
LDR PC, [pc, #24]
LDR PC, [pc, #24]
NOP ; Reserved Vector
; LDR PC, [pc, #24]
LDR PC, [PC, #-0xF20] ; Vector from AIC_IVR
; LDR PC, [pc, #24]
LDR PC, [PC, #-0xF20] ; Vector from AIC_FVR
Reset_Addr DCD __Soft_Reset
Undef_Addr DCD __Undef_Handler
SWI_Addr DCD __SWI_Handler
PAbt_Addr DCD __PAbt_Handler
DAbt_Addr DCD __DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD __IRQ_Handler
FIQ_Addr DCD __FIQ_Handler
.....
void __irq __Soft_Reset( void )
{
}
void __irq __Undef_Handler( void )
{
}
void __irq __SWI_Handler( void )
{
}
void __irq __PAbt_Handler( void )
{
}
void __irq __DAbt_Handler( void )
{
}
void __irq __IRQ_Handler( void )
{
}
void __irq __FIQ_Handler( void )
{
}
Any comments would be gratefully received.
Many thanks
Marcus.
.
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