Generating a Wrap transfer
- From: "Viswa" <daita@xxxxxxxxxxx>
- Date: 23 Aug 2006 06:43:03 -0700
I wish to implement an ARM wrap transfer as part of SoC Verification. I
am using an ARM926EJ-S as the ARM processor. For this, I was told that
I had to generate a cache miss and when this happens the ARM reads a
cache line and this is how I could generate a wrap transfer. The
following is the series of steps that I had implemented as part of
1. Disable the I, D Cache MMU.
2. Flush the TLB and I and D caches.
3. Clean the D caches.
4. Initialize the TTB register.
5. Program the AP, C/ B bits in the PTE
6. Fill the TTB L1 table with entries.
7. Set user defined base addresses which are cacheable / write
8. Initialize Domain Access control
9. Enable the I/ D cache, MMU.
The above were part of the boot code.
In the test case, I try to access the address which I have defined in
step 7. Initially I write to the address locations defined in Step 7.
As part of the read function, I am trying to access 8 words. As I have
to create a cache miss, instead of a accessing a page boundary(eg:
x00), I start accessing from some address location(eg x14). However,
the processor tries to access sequential memory locations which are not
written to earlier. Hence the wrap is not observed.
Could you please let me know if there is anything else that I would
need to know / do apart from what I have done above?
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