Re: Locking data and instruction cachelines

Neil Bradley wrote:
I am looking for a way to lock an instruction and data cache line for my interrupt vectors. I'm using an Intel PXA270 based ARM variant, and I noticed that the article about locking cache lines on ARM's web site seemed to indicate that one can only lock instruction cache lines on ARM9 variants, and it's not available on ARM7 variants (just ARM9):

http://www.arm.com/support/faqip/3714.html

And apparently the ARM7 can only lock data cache. Is this indeed the case? If so, major bummer! Thanks!

Neil,

as Paul pointed out you can't compare Intel's own implementation
of ARM architecture (StrongARM, XScale) with ARM's implementations
of ARM architecture (ARM7, ARM9, ARM10, ARM11, etc.).

XScale implements ARM v5TE architecture.

For your particular question about instruction locking look at
section 4.3.4 of Intel XScale Core Developer's Manual which you
will find on Intel web site.


Laurent
.

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