Re: Microcontroller suggestions

The AVR32 based AP7000 has 32 kB internal SRAM
16 + 16 kB Cache, runs at 166 Mhz and has the high speed USB device.
Will reach your 150 MIPS for critical loops since you can run from the
cache.
I assume you can lock the cache as well (did not check)

just to be pedantic ... is quoting your speed requirements in MIPS not
meaningless if comparing an ARM instruction set with an AVR32 (or any other
non ARM) instructions set.

Regards,
Richard.

http://www.FreeRTOS.org
*Now for ARM CORTEX M3!*



.

Relevant Pages

  • Re: Microcontroller suggestions
    ... I assume you can lock the cache as well ... meaningless if comparing an ARM instruction set with an AVR32 (or any ... other non ARM) instructions set. ... average or maximum MIPS is often quoted and is totally useless. ...
    (comp.sys.arm)
  • MIPS vs ARM architectures
    ... I've been curious about the relative merits of ARM and MIPS and just ... I was under the impression that ARM's instruction set allows for denser ...
    (comp.arch.embedded)
  • Re: Forth on the Maximite
    ... on the famous MIPS architecture. ... Paul, I was wondering, too, because I like the ARM micro and I ... that leaves the PIC32 out entirely! ...
    (comp.lang.forth)
  • Re: Forth on the Maximite
    ... No it is not a reason to change, in fact, I find it to be fairly ... architecture is not a good one so that newbies would be much better ... It is a MIPS micro. ... But still for me the ARM was the better architecture - I had a project ...
    (comp.lang.forth)
  • Re: ARM926 caching question
    ... this question is for ARM experts, in particular it's about ARM926 core ... I want to use cache for speeding up processing on video buffer of size ... MVA is made by appending a special field FCSE PID in CP15 reg. ... in kernel mode, and got inconsistent data in user-mode buffers; ...
    (comp.arch.embedded)