Re: FIQ's and IRQ's



sunil wrote:
> Can anybody tell me how exactly FIQ's differ from IRQ's. I know
> that two IRQ's doesn't occur at a time. Is it possible that an FIQ can
> occur when an IRQ is getting processed. If yes what action is taken?

An FIQ interrupt is higher priority than an IRQ, it has its own mode (and
therefore r13, r14 and spsr) and mask bit (CPSR[6]), which allows it to be
taken while an IRQ is being handled - the processor can store enough state
to enable the programmer to return to the IRQ handler after handling the
FIQ. Further, the extra banked registers and the address of the FIQ vector
allows the programmer to build systems for which the interrupt latency for
an FIQ is less than for an IRQ.

In a typical system there will be one FIQ (the highest priority or most
critical interrupt) source, and a number of IRQ sources, arbitrated by an
interrupt handler.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.


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