Re: 2e enhanced ROM listing

Alex Freed wrote:

Judging from your e-mail address you are closer to the source :)

Geographically at least - yes!

I'm happy to be corrected. If you have a document describing how to do the top level in Verilog, I'll appreciate the pointer very much.
It's just that all of the examples appear to have schematics as a top
level.

OK, you got me there. I've only done VHDL top level. But I can't see why it would be any different?!? It's been about a year since I used Altium Designer... in fact the last project started out in it but I switched to a native Xilinx ISE design when it wasn't meeting timing, so I could add some constraints...

I'll have to dig through my memory vault... actually IIRC both projects (there were 2 of them) originally had top-level schematics, and I converted them to VHDL. One was Xilinx, the other Altera, and I did the conversion only so I could use native tools...

You can take the output of the schematic compiler and simply add that to the project (copy it to the main source directory) in place of the schematic version. Then modify the contents to make it more "human readable". Is that Verilog or VHDL? Or can you choose? Even a VHDL top-level would be preferable to schematic for portability reasons...

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"
.

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