Re: Disk ][ on the IBM PC's parallel port - second try

On 7 Dez., 23:04, Linards Ticmanis <ticma...@xxxxxx> wrote:

How will the PC be able to detect the length of a byte (8, 9 or 10
bits)? IMHO this is a must.

I don't think so. There is no mechanism to detect that, and this is
not needed. The Disk ][ doesn't detect it either.
It only has to be ensured that the data is shifted until the high bit
is set.
This is what the circuit does.
For copying protected disks, it might be required. But I don't have
any so I didn't care.
But one could simply hook a 4-bit-counter to the clock and reset lines
of the shift register (the '299) to count the number of bits shifted
in.
another latch would be needed then, too.
Though admittedly I'm not so sure I understand your circuit in the first
place.
Well, I don't think it's that complicated (except for the clock
regeneration, which is a little tricky):
A Shift register, and data latch(which could be left out) and some
logic to trigger the data latch and send a flag to the PC.
The clock regeneration circuit actually abuses a bug in the 555 which
is not really documented in the data sheet. It can be seen in some
waveforms though.
When RESETing the timing cap is discharged to 0 volts instead of 1/3
Vcc. So the time to recover from a RESET will be longer than the usual
cycle time (by 37%, if I figured it out correctly).
As long as the read data input is zero, the 555 will oscillate at
250kHz shifting in zeroes.
If a one is read there will be a pulse in the middle of the bit cell
resetting the 555. At that time the 555's output will go low clocking
the shift register shifting in a one. If I did everything right,
oscillation should restart 6 µs after reading the one, i.e. at the end
of the next bit cell.
If the one reached the 8th bit, the latch is clocked (with a little
delay by C1/R1 to meet the setup time). After a longer delay provided
by C2/R2 the shift register is cleared and is ready for the next byte.
The PC can then read the byte until the next is ready.

--
Ferdinand
.

Relevant Pages

  • Re: What is the basis on flip-flop replaced by a latch
    ... I am really interested in the theoritic bases of how a latch circuit ... Optimizing clock crossing and data path latency ... recognizes and latches ODT activation signals that are received on ODT ...
    (comp.arch.fpga)
  • Re: Single pin to control a shift register
    ... If there's a duplicate thread, ... I have an 8-Bit shift register chip, and at any time there will ... Each shift-register pin will go to a single LED, ... and the second pin would go to the clock input on ...
    (comp.arch.embedded)
  • Re: Spartan3 SRL16 + SliceFF, LUT stability
    ... polarity must be the same for both, SRLs and FFs). ... The LUT memories act ... shift register tap value results in an immediate change ... to the output without regard for the clock. ...
    (comp.arch.fpga)
  • Re: Avoiding meta stability? No where in this thread...
    ... it is logically indistinguishable from a shift register. ... this is a two stage synchronizer. ... The "clock it on the falling edge" ... circuit saves 1/2 a cycle in synchronizer latency, ...
    (comp.arch.fpga)
  • SPI on the User Port ... Mode Hang-Ups.
    ... SCLK: the serial clock ... SPI devices are byte-wide, but some are 16-bits wide, and some Digital/ ... the interface is often little more than a serial shift ... counter to trigger a write of data to the shift register and/or read ...
    (comp.sys.cbm)