Re: RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

Jorge Chamorro Bieling wrote:

1.- Think of page 0 addresses as registers, you should put them where
they belong: inside the processor, not in memory.

There's a couple of problems here. For one, page 0 is still addressable
memory so you'd have to implement the other load/store functions in a
pretty funky way to avoid issues here. Two, Any Apple II after the ][+
has at least two zero pages (Auxiliary memory) and in the case of
extended memory cards, many many more.

2.- The same goes for the stack. Can it be a set of 256 registers ?
PHA would take 1 cycle instead of 2.

Ditto the stack...

3.- If the memory bus was three bytes wide, a single cycle can present
to the processor both the opcode and the data in a single cycle. This
alone is a 2X,3X speedup, or no speedup at all if the instruction was 1
byte long... And it's quite easy to implement. It is left to the reader
as an exercise :-)

This would be a cute optimisation for acceleration mode to have,
effectively providing prefetch, however it would need to be disabled
for the C000-CFFF region or machine IO would behave very strangely.

I wonder whether it's worth it in the end. If it were me, my approach
would be to drop a DRAM controller on the FPGA, add 16meg via an
appropriate SIMM. I'd stick with cycle accurate reimplementation of the
65C02 and implement the Apple II peripheral bus at 1mhz timing. The
actual DRAM would run as fast as the core can cope with (50Mhz should
be easy) and 1mhz 'emulation' would be handled by waiting at the end of
instruction completion. The RAM would behave as does a RamWorks card,
eliminating the need for the clone to have an auxiliary slot. I'd
possible integrate USB host support via a core swiped from the
opencores project, and use that to implement high-speed storage via
memory sticks. It'd live in pseudo slot-7 using a similar scheme that
the IIGS uses to allow both internal devices and slots.

This whole thing would live on a board form factor compatible with a
standard Apple IIe case and power supply, by reprogrammable via a
simple cable and have lots of additional header pins in unclaimed board
space so that over time, more peripheral cards could be replaced with
FPGA logic.

I would think that the speed achievable using FPGA with the RAM
subsystem operating at the 'accelerated' speed would be more than
adequate. I'd consider anything more than 16Mhz to be a bonus, because
really, ALL Apple II software would absolutely scream at this speed,
especially as it's a lot faster than any accelerator has ever achieved,
and for the most part, nobody is going to write software that depends
on the performance anyway.

Of course, if someone manages to hit 50Mhz or more I'd be most
impressed, and be first in line to purchase a couple of these things so
I can finally retire my aging and very difficult/expensive to replace
'production' Apple IIe

Matt

.

Relevant Pages

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