RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

**** SOME IDEAS FOR THE APPLE II FPGA'ers ****

There are things that should better not be copied from the original 6502
design. No matter what max. clock speed you achieve in your fpga
development, avoiding these bottleneck will at least *double* the end
performance.

Whatever instruction it executes, the number of memory cycles is a major
speed limiting factor in the 6502. The shortest instruction takes 2
cycles (speed factor : 1/2 = 50%) the longest takes 6-7 cycles (speed
factor = 1/6 = 16%).

So, getting the most of each and every memory cycle, or avoiding them at
all if possible makes a BIG difference.

I think it is possible, and these are the ideas I had:

1.- Think of page 0 addresses as registers, you should put them where
they belong: inside the processor, not in memory. This way you can avoid
all page 0 related memory cycles. For example, Zero Page Indirect
addressing modes benefit of two memory cycles of speed increase, LDA
($80) requires one memory cycle to fetch the the LDA opcode, another to
read the $80, yet another TWO to read the address in memory locations
$80,$81. This way it would take 3 cycles instead of 5.

2.- The same goes for the stack. Can it be a set of 256 registers ?
PHA would take 1 cycle instead of 2.

3.- If the memory bus was three bytes wide, a single cycle can present
to the processor both the opcode and the data in a single cycle. This
alone is a 2X,3X speedup, or no speedup at all if the instruction was 1
byte long... And it's quite easy to implement. It is left to the reader
as an exercise :-)

All applied, LDA($80) would take 1 cycle instead of 5. Think of it this
way: If the processor you developed ran at a max clock of 50 MHz, this
way it would execute this instruction as if the clock speed was 50*(5/1)
= 250Mhz ...!

What do you think ?
--
Jorge Chamorro Bieling
.