Re: How does the ZIP chip work?
- From: "Michael J. Mahon" <mjmahon@xxxxxxx>
- Date: Wed, 11 Jan 2006 17:42:13 -0800
Bryan Parkoff wrote:
"Michael J. Mahon" <mjmahon@xxxxxxx> wrote in message news:7JSdnSAJ-6865FjenZ2dnUVZ_s-dnZ2d@xxxxxxxxxxxxxx
Bryan Parkoff wrote:
"Michael J. Mahon" <mjmahon@xxxxxxx> wrote in message news:-q6dnQri-J64w1jenZ2dnUVZ_t-dnZ2d@xxxxxxxxxxxxxx
Jorge Chamorro Bieling wrote:
Eric <englere.geo@xxxxxxxxx> wrote:
I've been wondoring how the ZIP chip can speed up an Apple IIe. I understand it has a 4 Mhz 65C02 and it plugs into the original 6502 socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm rounding to 1 Mhz to make it easier to discuss) to access memory because the video refresh circuit uses the other half. So, the orig 6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can only speed up that part of the 1 Mhz cycle that is not used for video refresh. Assuming main memory could run 4X faster (which it can't), then it could bring that 500ns down to maybe 125ns. This means the overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some kind of cache? What am I missing here?
Yes, the zipchip has internal ram. It caches as much as it can. Once in the cache, it does not need to access the mainboard ram for reading/fetching/executing, only for writes and only if the write goes to the screen buffers ot the i/o addresses (of course i/o addresses are always read from the a2 mainboard). Also, there's a potential problem with ram expansion cards (whose "pages" overlap the rom addresses) which are activated using different addresses/schemes so you can tell the zipchip to enable/disable caching for rom addresses($D000-FFFF). It seems to me that the $c800-cfff range is also never cached as my videx does not speed up much. The same goes individually for each slot's rom addresses because some cards use the slot's rom address for i/o (the videx screen buffer is a good example of this, starting at $cc00). To deal with critical timing loops as is the case with diskII i/o, you can configure it to switch to normal (1MHz) speed for "a while" when accessing whichever slot (you usually set this only for slot 6). The last zipchips ran at 8MHz internally..! and it looks like there were even 10MHz rocketchips (I've never seen one).
No, the Zip Chip is strictly write-through. All writes slow down and go to Apple RAM (or whatever). There is no "dirty" bit in the cache tag RAM. To delay writes would complicate cache misses a great deal and would have to be defeated in any case for graphics and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is not tracked by the Zip Chip. The I/O expansion ROM area ($C800.. $CFFF) is an example of this. It does, however, track the bank switching in RamWorks-type expansion cards up to 2MB. This limit is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K) address bits, plus up to 5 bits for RAM card bank. 32 banks of 64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the main board.
The Zip can be configured to slow down to 1MHz (run synchronously) for several kinds of references. The slot I/O addresses are the most commonly stated, but the speaker address and the paddle trigger are a couple of others. When a "slow mode" slot /DEVSEL address is referenced, the Zip resets an internal 53 millisecond timer. It resumes accelerated execution when that timer times out.
-michael
Music synthesis for 8-bit Apple II's! Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design tool--and it is seriously underused."
Michael,
Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run at 14MHz without using accelerator? Let say 14,318,180 crystal osc is on motherboard. Video scanner depends on 14M crystal osc chip to run at 1MHz and RAM runs at 2MHz. We may change the logic on the motherboard so CPU will run at 14MHz while "load/shift bit for video" is performed at the same time. We can add switch like dip box to switch from 14MHz to original 1MHz. Cache and internal memory like Zip chip or Transwarp card may not be needed.
Do you expect that it will work if we modify the logic on the motherboard to manipulate 14M crystal osc chip?
No. The entire timing design of the Apple II is predicated on the processor interface running at 1MHz. That's why all accelerators that run using the processor interface do so with caching and bus synchronization logic. Any time they interface with the Apple II, they do so at the 1MHz speed.
-michael
Music synthesis for 8-bit Apple II's! Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design tool--and it is seriously underused."
Michael,
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to the CPU design? It does not make sense because it can handle maximum 14MHz like WDC 65816 CPU chip. Nintendo NES and sNES run at approximately less than 2MHz. Apple IIgs with 28M crystal osc runs at 2.5MHz without using accelerator card. If you rewire 6502 CPU to 14M crystal osc by modifying timing logic, it might work without accelerator card.
Notice I didn't say anything at all about limits on the speed of a CPU, only limits on the speed at which a CPU can interface with the Apple--a limit imposed by the Apple II design which was very appropriate when the Apple II was designed, and around which the entire system was implemented.
During each cycle (about 1 microsecond), the Apple II memory services at most two requests--a read from the video generator, and a read or write from the 65(C)02 CPU. There is no way within the design to accomodate more than these two memory accesses, since they may even be to the same location.
As a result, any accelerator must design a mechanism for the faster CPU of the accelerator to synchronize with the Apple II bus and wait any response. What allows any accelerator to run faster than the Apple bus is the presence of fast memory which contains a copy of the Apple RAM data for the address(es) being referenced by the CPU. This is the "modified timing logic" that allows acceleration.
The fast CPU can then run at full speed so long as all of its memory needs are being met by the contents of the fast memory cache. Whenever it is necessary to get new information from Apple memory, or to send new data to Apple memory, the fast CPU must synchronize with the Apple bus (so that it is the CPU's turn to interact with memory) and slow down to receive or send data.
The effective speed of the fast CPU is the weighted average of its time running at high speed and its time running at 1MHz while synchronized with the Apple bus. Except for very special programs, this effective speed is seldom more than 60%-70% of a Zip Chip's speed. For example, an 8MHz Zip Chip-equipped machine runs typical software about 5x faster than stock 1MHz speed, for a 67% speedup.
-michael
Music synthesis for 8-bit Apple II's! Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design tool--and it is seriously underused." .
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