Re: questions about memory_order_seq_cst fence

Alexander Terekhov <terekhov@xxxxxx> writes:

Anthony Williams wrote:

Masakuni Oishi <yamasa@xxxxxxxxxxxx> writes:

If so, for the code 1 in my first post, is the outcome
r1 == 0 && r2 == 1 && r3 == 0 possible on IA-64?

I believe so.

Perhaps this is relevant:

See Total ordering of WB Releases.

The example is this:

/*** code 1 ***/
// Initially
atomic<int> x(0), y(0);

// Thread 1:, memory_order_release);
r1 = x.load(memory_order_acquire);

// Thread 2:, memory_order_release);

// Thread 3:
r2 = x.load(memory_order_acquire);
r3 = y.load(memory_order_acquire);

In the above code, is r1 == 0 && r2 == 1 && r3 == 0 possible?

Under the C++0x memory model, the acquire and release operations here
serve no purpose --- there are no stores prior to the releases, so there
is no imposed ordering, and they might as well all be

The above code is thus equivalent to the code below, as far as the C++0x
memory model goes, and the compiler would be conforming if it compiled
it as such:

// Initially
atomic<int> x(0), y(0);

// Thread 1:, memory_order_relaxed);
r1 = x.load(memory_order_relaxed);

// Thread 2:, memory_order_relaxed);

// Thread 3:
r2 = x.load(memory_order_relaxed);
r3 = y.load(memory_order_relaxed);

I am not an expert on IA-64, but I would expect a relaxed write on IA-64
to be plain ST --- an unordered write --- and a relaxed load to be a
plain LD --- an unordered read.

Given that, the total ordering of WB releases is not relevant here, and
I suspect that r1 == 0 && r2 == 1 && r3 == 0 is possible.

Author of C++ Concurrency in Action
just::thread C++0x thread library
Just Software Solutions Ltd
15 Carrallack Mews, St Just, Cornwall, TR19 7UL, UK. Company No. 5478976