Re: questions about memory_order_seq_cst fence




Anthony Williams wrote:

Alexander Terekhov <terekhov@xxxxxx> writes:

Anthony Williams wrote:

Masakuni Oishi <yamasa@xxxxxxxxxxxx> writes:

If so, for the code 1 in my first post, is the outcome
r1 == 0 && r2 == 1 && r3 == 0 possible on IA-64?

I believe so.

Perhaps this is relevant:

http://download.intel.com/design/itanium/downloads/25142901.pdf

See 3.3.7.1 Total ordering of WB Releases.

(remote write atomicity)

Maybe I'm wrong; I am not an expert on IA-64 semantics.

Suppose that I can program in terms of C++MM's acquire/release. The
platform is x86.

How am I supposed to ensure remote write atomicity ala IA-64 releases
for a particular store (relevant loads) using C++MM and NOT pessimizing
everything to seq_cst?

The next question is regarding store-load fencing for particular
release-store and subsequent acquire-load.

If both can not be done easily under C++MM then it is pretty useless to
me.

regards,
alexander.
.