Re: questions about memory_order_seq_cst fence

Alexander Terekhov <terekhov@xxxxxx> writes:

Anthony Williams wrote:

Masakuni Oishi <yamasa@xxxxxxxxxxxx> writes:

If so, for the code 1 in my first post, is the outcome
r1 == 0 && r2 == 1 && r3 == 0 possible on IA-64?

I believe so.

Perhaps this is relevant:

See Total ordering of WB Releases.

(remote write atomicity)

Maybe I'm wrong; I am not an expert on IA-64 semantics.

Author of C++ Concurrency in Action
just::thread C++0x thread library
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