Re: questions about memory_order_seq_cst fence

Anthony Williams wrote:

Masakuni Oishi <yamasa@xxxxxxxxxxxx> writes:

If so, for the code 1 in my first post, is the outcome
r1 == 0 && r2 == 1 && r3 == 0 possible on IA-64?

I believe so.

Perhaps this is relevant:

See Total ordering of WB Releases.

(remote write atomicity)