# Re: questions about memory_order_seq_cst fence

*From*: Anthony Williams <anthony.ajw@xxxxxxxxx>*Date*: Tue, 14 Jun 2011 23:05:57 +0100

Masakuni Oishi <yamasa@xxxxxxxxxxxx> writes:

/*** code 1 ***/

// Initially

atomic<int> x(0), y(0);

// Thread 1:

y.store(1, memory_order_release);

atomic_thread_fence(memory_order_seq_cst);

r1 = x.load(memory_order_acquire);

// Thread 2:

x.store(1, memory_order_release);

// Thread 3:

r2 = x.load(memory_order_acquire);

atomic_thread_fence(memory_order_seq_cst);

r3 = y.load(memory_order_acquire);

/***************/

In the above code, is r1 == 0 && r2 == 1 && r3 == 0 possible?

I think it should be prohibited, but I couldn't make sure that

from the C++0x FDIS.

Premise 1: r3 == 0.

Since the only store to y is the store of 1 by thread 1, r3 == 0 implies

that the load from y on thread 3 is reading the initial value of y.

29.3p6 of N3290 says:

"For atomic operations A and B on an atomic object M, where A modifies M

and B takes its value, if there are memory_order_seq_cst fences X and Y

such that A is sequenced before X, Y is sequenced before B, and X

precedes Y in S, then B observes either the eﬀects of A or a later

modification of M in its modification order."

If the fence in thread 1 precedes the fence in thread 3 in S, then the

read at r3 must therefore see the value written by the store in thread

1. Consequently, the fence in thread 3 must precede the fence in thread

1 in S.

Premise 2: r2 == 1.

The load of x in thread 3 reading 1 implies it has read the value of the

store to x from thread 2.

We already know that the fence in thread 3 precedes the fence in thread

1 in S.

29.3p7 of N3290 says:

"For atomic operations A and B on an atomic object M, if there are

memory_order_seq_cst fences X and Y such that A is sequenced before X, Y

is sequenced before B, and X precedes Y in S, then B occurs later than A

in the modification order of M."

In our case, the fence in thread 3 occurs before the fence in thread 1

in S. The fence in thread 3 is thus X, the fence in thread 1 Y, the read

from x in thread 3 is A and the read from x in thread 1 is B.

Thus the read of x in thread 1 must occur later in the modification

order of x than the read in thread 3. Since the read in thread 3 is of

the last store to x (1), the read in thread 1 must also read that value,

and r1 == 1.

Therefore r1==0, r2 == 1 and r3 == 0 is not possible.

So, my questions are:

For code 1, is r1 == 0 && r2 == 1 && r3 == 0 allowed in the C++0x

FDIS?

No.

Anthony

--

Author of C++ Concurrency in Action http://www.stdthread.co.uk/book/

just::thread C++0x thread library http://www.stdthread.co.uk

Just Software Solutions Ltd http://www.justsoftwaresolutions.co.uk

15 Carrallack Mews, St Just, Cornwall, TR19 7UL, UK. Company No. 5478976

.

**Follow-Ups**:**Re: questions about memory_order_seq_cst fence***From:*Chris M. Thomasson

**Re: questions about memory_order_seq_cst fence***From:*Joshua Maurice

**References**:**questions about memory_order_seq_cst fence***From:*Masakuni Oishi

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