# questions about memory_order_seq_cst fence

*From*: Masakuni Oishi <yamasa@xxxxxxxxxxxx>*Date*: Mon, 13 Jun 2011 09:40:30 -0700 (PDT)

Hi,

I have some questions about C++0x memory model.

/*** code 1 ***/

// Initially

atomic<int> x(0), y(0);

// Thread 1:

y.store(1, memory_order_release);

atomic_thread_fence(memory_order_seq_cst);

r1 = x.load(memory_order_acquire);

// Thread 2:

x.store(1, memory_order_release);

// Thread 3:

r2 = x.load(memory_order_acquire);

atomic_thread_fence(memory_order_seq_cst);

r3 = y.load(memory_order_acquire);

/***************/

In the above code, is r1 == 0 && r2 == 1 && r3 == 0 possible?

I think it should be prohibited, but I couldn't make sure that

from the C++0x FDIS.

So I changed the memory_order of Thread 2 to seq_cst, like this:

/*** code 2 ***/

// Initially

atomic<int> x(0), y(0);

// Thread 1:

y.store(1, memory_order_release);

atomic_thread_fence(memory_order_seq_cst); // (1)

r1 = x.load(memory_order_acquire);

// Thread 2:

x.store(1, memory_order_seq_cst); // (3)

// Thread 3:

r2 = x.load(memory_order_acquire);

atomic_thread_fence(memory_order_seq_cst); // (2)

r3 = y.load(memory_order_acquire);

/***************/

In code 2, r1 == 0 && r2 == 1 && r3 == 0 is not allowed.

The proof is as follows:

When (1) precedes (2) in S,

r3 == 0 is not allowed (FDIS 29.3_6).

When (2) precedes (1) in S,

if r2 == 1 then (3) happens before (2), so (3) precedes (2) in S,

therefore, (3) precedes (1) in S.

Then, r1 == 0 is not allowed (FDIS 29.3_4).

So, my questions are:

For code 1, is r1 == 0 && r2 == 1 && r3 == 0 allowed in the C++0x

FDIS?

If it is, is there any real architecture which allows such result?

-- masakuni

.

**Follow-Ups**:**Re: questions about memory_order_seq_cst fence***From:*Anthony Williams

**Re: questions about memory_order_seq_cst fence***From:*Joshua Maurice

**Re: questions about memory_order_seq_cst fence***From:*Edek

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