Re: Problem in accessing PCI I/O Registers in MPC8247
- From: "gvarndell" <gvarndell@xxxxxxxxxxx>
- Date: 30 Aug 2006 03:23:35 -0700
lichlin wrote:
gvarndell wrote:
lichlin wrote:
Hi All
I'm facing a problem in accessing my card's (PCI2IDE) registers. If
anyone of you could help me to fix this, it would be of great help.
I can scan the card in PCI bus.
==============================================================
Scanning function 0 of each PCI device on bus 0
Using configuration mechanism 0
bus device function vendorID deviceID class
00000000 00000000 00000000 00001057 000018c1 00060000
00000000 0000001a 00000000 00001283 00008212 00010400
==============================================================
The macro about PCI part:
/* PCI based addresses */
#define PCI_MEM_ADRS 0x80000000
#define PCI_MEM_SIZE 0x01000000 /*16MB */
#define PCI_MEM_SIZE_MASK PCI_SIZE_MASK_16M
#define PCI_MEMIO_ADRS 0x90000000
#define PCI_MEMIO_SIZE 0x01000000 /*16MB */
#define PCI_MEMIO_SIZE_MASK PCI_SIZE_MASK_16M
#define PCI_IO_ADRS 0xa0000000
#define PCI_IO_SIZE 0x00100000 /* IO Space is not available */
/* CPU based addresses */
#define CPU_PCI_MEM_ADRS PCI_MEM_ADRS
#define CPU_PCI_MEM_SIZE PCI_MEM_SIZE
#define CPU_PCI_MEMIO_ADRS PCI_MEMIO_ADRS
#define CPU_PCI_MEMIO_SIZE PCI_MEMIO_SIZE
#define CPU_PCI_IO_ADRS PCI_IO_ADRS
#define CPU_PCI_IO_SIZE PCI_IO_SIZE
And CPU_PCI_MEM_ADRS, CPU_PCI_MEMIO_ADRS, CPU_PCI_IO_ADRS ware added
into the struct sysPhysMemDesc[] in file syslib.c. Use
sysPciAutoConfig(). But when i use sysOutByte() and sysInByte() or W/R
of memory directly to access the io registers of PCI, the exception
occurs.
For example:
sysOutByte( CPU_PCI_IO_ADRS+reg, value );
or
value = *(char *)(CPU_PCI_IO_ADRS+reg);
In the future, please specifiy which vxWorks version you're using.
You're assuming your device was assigned the base address of IO space
-- probably not.
Use pciConfigTopoShow or pciHeaderShow to see if/how that PCI BARs were
setup by auto config.
This will tell you where the device's mem and IO spaces actually are.
Once you know that, you may be done -- but there could be other
problems.
GV
Thank you very much, GV
My vxworks' version is 5.5.
And the print message of pciConfigTopoShow() is followed:
===============================================================
[0,0,0] type=HOST BRIDGE
status=0x20b0 ( CAP 66MHZ FBTB DEVSEL=0 MSTR_ABORT_RCV )
command=0x0006 ( MEM_ENABLE MASTER_ENABLE )
bar0 in 32-bit mem space @ 0x40000000
bar1 in prefetchable 32-bit mem space @ 0x00000000
[0,26,0] type=MASS STORAGE
status=0x0230 ( CAP 66MHZ DEVSEL=1 )
command=0x0005 ( IO_ENABLE MASTER_ENABLE )
bar0 in I/O space @ 0xf0000000
bar1 in I/O space @ 0xf0000008
bar2 in I/O space @ 0xf0000010
bar3 in I/O space @ 0xf0000018
bar4 in I/O space @ 0xf0000020
===============================================================
And pciHeaderShow(0,0x1a,0):
===============================================================
vendor ID = 0x1283
device ID = 0x8212
command register = 0x0005
status register = 0x0230
revision ID = 0x13
class code = 0x01
sub class code = 0x04
programming interface = 0x00
cache line = 0x00
latency time = 0x40
header type = 0x00
BIST = 0x00
base address 0 = 0xf0000001
base address 1 = 0xf0000009
base address 2 = 0xf0000011
base address 3 = 0xf0000019
base address 4 = 0xf0000021
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0000
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x01
interrupt pin = 0x01
min Grant = 0x08
max Latency = 0x08
==========================================================
I know the value of BARx, but i cannot do access to IO space. If i want
to write/read IO address 0xf0000001, how to do? I use sysOutByte(
0xf0000001, 0x99) , but exception occurs.
The LSB of a BAR means I/O -- it's not part of the address.
Some of the high order bits are not part of the address either.
Try putting some other device on the PCI bus, one with memory BARs.
You might discover something that will help you figure it out.
I don't think your host bridge is properly configured, which is a not a
problem that is well suited to solution by google posts.
GV
.
- References:
- Problem in accessing PCI I/O Registers in MPC8247
- From: lichlin
- Re: Problem in accessing PCI I/O Registers in MPC8247
- From: gvarndell
- Re: Problem in accessing PCI I/O Registers in MPC8247
- From: lichlin
- Problem in accessing PCI I/O Registers in MPC8247
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