Re: Connecting an inout port to another inout port



On Aug 10, 6:28 pm, Mike Treseler <mtrese...@xxxxxxxxx> wrote:
THurkmans wrote:
I am trying to avoid signals when I can. I use them in port maps, and
use a two processes approach for other logic. The thing is that this
translate-block requires to select certain port maps and output them
differently at the outputs. For example, input a can become output b,
c or d. The solution I know for this requires an intermediate signal
for the actual selection. Is there another way?

multiple signals in an architecture is analogous to
multiple variables in a process
for the purposes of logic description.
for example, see:

http://mysite.verizon.net/miketreseler/stack.vhd
http://mysite.verizon.net/miketreseler/stack.pdf

     -- Mike Treseler

Thanks for the example. It is a more elaborate template than the one I
was using.

So if it is analogous, and signals in an architecture don't solve the
problem of an additional delta delay, how can variables in a process
solve it instead?
.



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