Re: Simulating Inverted Registers
- From: Shannon <sgomes@xxxxxxxxxxxxx>
- Date: Tue, 30 Jun 2009 14:04:12 -0700 (PDT)
On Jun 30, 1:48 pm, Shannon <sgo...@xxxxxxxxxxxxx> wrote:
Seems like I'm posting a lot lately. I really appreciate all the help
you guys have given. You are helping bring me up to speed quickly.
On to the question....
Although my question is about simulation, this concerns a design for
synthesis.
I have a 32-bit register that I load a default value into during
reset. As Altera has explained to me, the hardware can only pre-load
zeros. To get a '1' bit they put inverters on each side of the flip-
flop and force it clear. Ok I get that.
In actuality the "inverters" don't really exist. They get pushed into
the surrounding logic. So when I simulate using Quartus's simulator
or ModelSim I probe my register and I get some inverted bits.
(corresponding to where the ones are in my default value).
I've tested the real hardware and it works fine. I know I'm not the
first person to load a default value into a register. Is there a
"standard" way of dealing with this in simulation? I have lots of
ideas but they all seem kludge-y. I suspect there is some common ways
of dealing with it.
I hope I've explained the situation clear enough.
Thanks,
Shannon
Here is a complete entity that simulates what I'm talking about:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity inverted is
port
(
reset : in std_logic;
clk : in std_logic;
byte_out : out std_logic_vector(7 downto 0)
);
end inverted;
architecture rtl of inverted is
signal byte : unsigned(7 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
byte <= X"42"; --arbitrary number for example
elsif rising_edge(clk) then
byte <= byte + 1;
end if;
end process;
byte_out <= std_logic_vector(byte);
end rtl;
In this example byte_out will simulate exactly as you would expect -
starting off at 42h and counting up each clock. "byte" however will
not simulate as you would expect. Well at least not how "I" would
expect. lol
Shannon
.
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- Simulating Inverted Registers
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