Re: So, they started synthesizing shared variables?

Andy,
I also read your related paper. Your model in section 6.1 of the
behavior of a dual edged flop is flawed. An asynchronous reset should
be the highest priority (not an elsif to the clock conditions), as is
correctly mentioned in section 2.1.
The implementation you expected is in the slides. The one from the
paper
is still correct as it uses nReset as inactive as a condition to the
clock
statements - which is permitted in 1076.6-2004 - looking back I have
no
idea why I would have written the paper that way.

Also, with two simultaneous
clocks, it is a bit pessimistic. The output should not assume 'X'
unless the two data inputs are different and reset is not asserted.
The example was intended to show that one can detect and flag
simultaneous changes if it is problematic for the circuit being
created, however, one is not obliged to do this.

But relax, I'm not insulted by your ignorance... :^) Seriously, I
truly enjoy and respect your fervent advocation of VHDL, whether I
agree with all of it or not.
The standard gives users something to ask your vendor to implement.
If you ignore it, then we get stuff that may solve the issue, however,
in this case is not VHDL compliant. Not great, but like
Mike T noted, one does have to get a job done.

I believe the 1999 approach (not the content) of the standard is more
useful than apparently that of the 2004 standard. ...
WRT support and not support, the 2004 approach is identical to the
1999 approach. I think the selective quoting and confusion introduced
since the standard is for both writing compliant
models and writing compliant tools.

The quote from, Matthew Hicks, which states:
IEEE 1076.6 states, "The intent of this version was to include a maximum
subset of VHDL that could be used to describe synthesizable RTL logic."

This is correct, however, it was in the introduction which was noted
as
"not part of IEEE Std 1076.6-2004". Meaning it is non-binding.

I find the word maximum easy to misunderstand here. I think the
working
group was trying to say that the goal was to maximize the variations
of
coding styles that would be accepted by a compliant synthesis tool.
To do this, the 1999 templates for flip-flops were replaced by rules
that included the templates and more.

To further clarify this, the Scope of the 2004 specification states:
---------------------------------- Start of Quote of 2004
specification --------------------------
1.1 Scope
This standard defines a subset of very high-speed integrated circuit
hardware description language (VHDL)
that ensures portability of VHDL descriptions between register
transfer level synthesis tools. Synthesis tools
may be compliant and yet have features beyond those required by this
standard. This standard defines how
the semantics of VHDL shall be used, for example, to model level-
sensitive and edge-sensitive logic. It also
describes the syntax of the language with reference to what shall be
supported and what shall not be supported
for interoperability.
---------------------------------- End of Quote of 2004 specification
--------------------------
My interpretation is that a synthesis vendor is permitted to do more
than the standard states.

We also need to address what not supported means, so
moving on to the next quote also from Matthew:
By the way, if you look at the synthesis standards for VHDL (IEEE 1076.6-2004)
it clearly says shared variables aren't supported. So a designer shouldn't
be using them even if tool support is there.

While this is true, one has to review what "not supported" means:
---------------------------------- Start of Quote of 2004
specification --------------------------
Not Supported: RTL synthesis does not support the construct. RTL
synthesis does not expect to
encounter the construct, and the failure mode shall be undefined. RTL
synthesis may fail upon
encountering such a construct. Failure is not mandatory; more
specifically, RTL synthesis is allowed
to treat such a construct as ignored.
NOTE—A synthesis tool may interpret constructs that are identified as
not supported in this standard. However a model
that contains such unsupported constructs is not compliant with this
standard.
---------------------------------- End of Quote of 2004 specification
--------------------------
My interpretation is that a synthesis tool vendor is permitted to
support anything
it likes that is labeled as not supported and still be compliant, but
a model that
uses constructs marked as not supported is not compliant with the
standard.


Although I worked on both the 1999 and 2004 committees, this is not an
official
interpretation of the standard. If you need an official
interpretation, you can
request this by contacting the chair of the sponsoring committee of
standard. The
sponsoring committee for both 1076.6 and most IEEE EDA standards is
DASC. You can
find DASC on the web at: http://www.dasc.org/

Cheers,
Jim
.

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