Re: Multiple components driving a single bus
- From: Brian Drummond <brian_drummond@xxxxxxxxxxxxx>
- Date: Wed, 22 Apr 2009 08:05:49 +0100
On Tue, 21 Apr 2009 18:27:42 -0700 (PDT), Benjamin Couillard
<benjamin.couillard@xxxxxxxxx> wrote:
Hi, I've got a question for you guys.....
Let's say I've got 2 blocks that can drive one bus (but there could be
more).
Block1 : Block
generic map (Address => x"000")
port map (CLK => CLK,
ADDR => ADDR,
BUS_STB => BUS_STB,
RD_WR_N => RD_WR_N,
DATA_OUT => BUS_DATA,
....);
Block2 : Block
generic map (Address => x"004")
port map (CLK => CLK,
Let's say that when the address is not 0, DATA_OUT of block1 will be
high-Z and when the addres is not 4 Data_out of block 2 will be high-
Z. Will ISE synthesis engine be smart enough to realize there is no
bus contention? Basically, will ISE infer muxes from that code?
Look in the synthesis report for warnings that tri-states have been replaced by
muxes.
Any time I've tried it, it has worked - but XST will complain about it.
This ssumes ADDR is internal. If ADDR goes off chip, the synth tool can't
analyse the outside world. It may be smart enough to infer MUXes internally and
tristates on the I/O pins but I haven't verified that.
- Brian
.
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- Multiple components driving a single bus
- From: Benjamin Couillard
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