Re: How do variables get synthesized in this case?

On 18 Mar, 15:05, Martin Thompson <martin.j.thomp...@xxxxxxx> wrote:
Jacko <jackokr...@xxxxxxxxx> writes:
On 16 Mar, 23:19, Jonathan Bromley <jonathan.brom...@xxxxxxxxxxxxx>
wrote:
On Mon, 16 Mar 2009 15:50:35 -0700 (PDT), Jacko wrote:

[incomplete sensitivity list]

implies simulation will be differnt from produced logic,

Indeed. That fits my understanding of Bloody Stupid
pretty well.

Just because simulation is lazy by not actually simulating the
netlist, you assume much.

Isn't that backwards? VHDL is a simulation language. You simulate
your code until it works.

In this case you will be suprised about the number of possible logic
transitions on any signal, when the do not propergate to change the
state of another signal. Most sythesizers will generate the logic
which has the extra state changes of signals (as it is easier).

Then you run a synthesiser over the same code and it produces you a
netlist which (in theory) matches your code that you so carefully
wrote and verified.

It will match your code in boolean logic function of registered values
if all critical sensitivities are included. It may not match your code
if you miss one, hence the warning. All non critical ones may produce
a warning, but would not change the functioning of the code.

So there are 3 types of referred to signal.

process(clk)
fart <= smelly;
nose <= fn(fart);
end process;

in this instance having fart in the sensitivity list is pointless but
still makes a warning.

with process(clk,smelly) everything will simulate correctly but still
cause a warning.

with process(clk,fart) changes in smelly would not be relevant, and
could be register delayed through clk.

(Clearly the word "you" in the above should be replaced by "other
engineers", or indeed "I" :)

If the synth doesn't translate that code into a functionally
equivalent netlist, how is that the simulator's fault? Of course we
just have to work with the fact that synth tools do what they do,
which leads me to avoid non-clocked processes wherever possible, but I
don't have to like it, or try and make out it's the way things
"should" work.

There are always going to be things that simulate that the synth can't
turn into a netlist, but is it valid for it just to go "well, here's
something a bit like it" flag a quick warning (in amongst a morass of
other warnings) and call "job done".

<rant>
And the example under discussion isn't even one where the synth-tool
*can't* do the job conforming to the language spec, it just chooses
not to! It's like a C-compiler changing 'i++' to '++i' "because
that's usually what people want to happen when they write that".
</rant>

umm.

All reasonable sythesis
tools produce logic as though they had been included in the
sensitivity list,

All tools I know do so, and produce a warning message
precisely because it is not "reasonable".

No, because it may not be what is expected. It may be reasonable.

Why is it reasonable to not work as the language spec defines it?

No. "why is it reasonable? *reasonable??* well you write the b**tard
thing then!!" :-)

It may be reasonable to want such registration of values to prevent
such signal oscillation for power saving reasons, hence REASONable.

cheer jacko
.

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