Re: any way to avoid warnings about unused outputs in XST?

Mike Treseler wrote:

Ken Cecka wrote:

I'm not sure I understand the difference - how do I go about using a
direct instance?

here's one:

dut : entity work.uart
generic map (char_len_g => tb_char_g, -- for vsim command line
overload
tic_per_bit_g => tb_tics_g)
port map (
clock => clk_s, -- [in] -- by tb_clk
reset => rst_s, -- [in] -- by tb_clk
address => address_s, -- [in] -- by main
writeData => writeData_s, -- [in] -- by main
write_stb => write_stb_s, -- [in] -- by main
readData => readData_s, -- [out]-- by uut
read_stb => read_stb_s, -- [in] -- by main
serialIn => serialIn_s, -- [in] -- by main,loopback
destination
serialOut => serialOut_s -- [out]-- by uut, loopback source
);

Just found a previous post from you on the subject:
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/6776632c8f686e91#c951a3ca8311ccc4

Apparently I've been spending all this time keeping component declarations synced up with my entities out of pure masochism :(

I'll definitely be making more use of direct instantiation, but it doesn't seem to solve the unused output warning. The example below (with or without the z line commented) generates an unconnected output warning.

Ken

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY foo IS
PORT
(
x : IN STD_LOGIC;
y : OUT STD_LOGIC;
z : OUT STD_LOGIC
);
END foo;

ARCHITECTURE model OF foo IS
BEGIN
y <= x;
z <= NOT x;
END;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY tmp IS
PORT
(
x : IN STD_LOGIC;
y : OUT STD_LOGIC;
z : OUT STD_LOGIC
);
END tmp;

ARCHITECTURE model OF tmp IS

BEGIN

FOO1 : ENTITY WORK.foo
PORT MAP
(
x => x,
y => y
--z => OPEN
);
z <= '0';

END;

.

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